Commit 015e7058 authored by Marek Szyprowski's avatar Marek Szyprowski Committed by Sylwester Nawrocki
Browse files

clk: samsung: remove __clk_lookup() usage 



__clk_lookup() interface is obsolete, so remove it from the Samsung clock
drivers. This has been achieved by getting rid of custom _get_rate()
helper and replacing it with clk_hw_get_rate().

Signed-off-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20211018125456.8292-2-m.szyprowski@samsung.com


Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
parent d68f50e6

drivers/clk/samsung/clk-exynos4.c

+10 −8
Original line number Original line Diff line number Diff line
@@ -437,7 +437,7 @@ static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = { 




/* list of mux clocks supported in exynos4210 soc */

/* list of mux clocks supported in exynos4210 soc */

static const struct samsung_mux_clock exynos4210_mux_early[] __initconst = {

static const struct samsung_mux_clock exynos4210_mux_early[] __initconst = {

	MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),

	MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),

};

};





static const struct samsung_mux_clock exynos4210_mux_clks[] __initconst = {

static const struct samsung_mux_clock exynos4210_mux_clks[] __initconst = {
@@ -603,7 +603,7 @@ static const struct samsung_div_clock exynos4_div_clks[] __initconst = { 
	DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),

	DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),

	DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),

	DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),

	DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),

	DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),

	DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),

	DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),

	DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),

	DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),

	DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),

	DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),

	DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),

	DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
@@ -1254,21 +1254,21 @@ static void __init exynos4_clk_init(struct device_node *np, 
		samsung_clk_register_mux(ctx, exynos4210_mux_early,

		samsung_clk_register_mux(ctx, exynos4210_mux_early,

					ARRAY_SIZE(exynos4210_mux_early));

					ARRAY_SIZE(exynos4210_mux_early));





		if (_get_rate("fin_pll") == 24000000) {

		if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) {

			exynos4210_plls[apll].rate_table =

			exynos4210_plls[apll].rate_table =

							exynos4210_apll_rates;

							exynos4210_apll_rates;

			exynos4210_plls[epll].rate_table =

			exynos4210_plls[epll].rate_table =

							exynos4210_epll_rates;

							exynos4210_epll_rates;

		}

		}





		if (_get_rate("mout_vpllsrc") == 24000000)

		if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24000000)

			exynos4210_plls[vpll].rate_table =

			exynos4210_plls[vpll].rate_table =

							exynos4210_vpll_rates;

							exynos4210_vpll_rates;





		samsung_clk_register_pll(ctx, exynos4210_plls,

		samsung_clk_register_pll(ctx, exynos4210_plls,

					ARRAY_SIZE(exynos4210_plls), reg_base);

					ARRAY_SIZE(exynos4210_plls), reg_base);

	} else {

	} else {

		if (_get_rate("fin_pll") == 24000000) {

		if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) {

			exynos4x12_plls[apll].rate_table =

			exynos4x12_plls[apll].rate_table =

							exynos4x12_apll_rates;

							exynos4x12_apll_rates;

			exynos4x12_plls[epll].rate_table =

			exynos4x12_plls[epll].rate_table =
@@ -1344,9 +1344,11 @@ static void __init exynos4_clk_init(struct device_node *np, 
	pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"

	pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"

		"\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",

		"\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",

		exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",

		exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",

		_get_rate("sclk_apll"),	_get_rate("sclk_mpll"),

		clk_hw_get_rate(hws[CLK_SCLK_APLL]),

		_get_rate("sclk_epll"), _get_rate("sclk_vpll"),

		clk_hw_get_rate(hws[CLK_SCLK_MPLL]),

		_get_rate("div_core2"));

		clk_hw_get_rate(hws[CLK_SCLK_EPLL]),

		clk_hw_get_rate(hws[CLK_SCLK_VPLL]),

		clk_hw_get_rate(hws[CLK_DIV_CORE2]));

}

}

drivers/clk/samsung/clk-exynos5250.c

+5 −5
Original line number Original line Diff line number Diff line
@@ -239,7 +239,7 @@ static const struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __ 
};

};





static const struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initconst = {

static const struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initconst = {

	MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),

	MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),

};

};





static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {

static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {
@@ -351,7 +351,7 @@ static const struct samsung_div_clock exynos5250_div_clks[] __initconst = { 
	 */

	 */

	DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),

	DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),

	DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),

	DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),

	DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),

	DIV(CLK_DIV_ARM2, "div_arm2", "div_arm", DIV_CPU0, 28, 3),





	/*

	/*

	 * CMU_TOP

	 * CMU_TOP
@@ -801,12 +801,12 @@ static void __init exynos5250_clk_init(struct device_node *np) 
	samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks,

	samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks,

				ARRAY_SIZE(exynos5250_pll_pmux_clks));

				ARRAY_SIZE(exynos5250_pll_pmux_clks));





	if (_get_rate("fin_pll") == 24 * MHZ) {

	if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) {

		exynos5250_plls[epll].rate_table = epll_24mhz_tbl;

		exynos5250_plls[epll].rate_table = epll_24mhz_tbl;

		exynos5250_plls[apll].rate_table = apll_24mhz_tbl;

		exynos5250_plls[apll].rate_table = apll_24mhz_tbl;

	}

	}





	if (_get_rate("mout_vpllsrc") == 24 * MHZ)

	if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24 * MHZ)

		exynos5250_plls[vpll].rate_table =  vpll_24mhz_tbl;

		exynos5250_plls[vpll].rate_table =  vpll_24mhz_tbl;





	samsung_clk_register_pll(ctx, exynos5250_plls,

	samsung_clk_register_pll(ctx, exynos5250_plls,
@@ -855,6 +855,6 @@ static void __init exynos5250_clk_init(struct device_node *np) 
	samsung_clk_of_add_provider(np, ctx);

	samsung_clk_of_add_provider(np, ctx);





	pr_info("Exynos5250: clock setup completed, armclk=%ld\n",

	pr_info("Exynos5250: clock setup completed, armclk=%ld\n",

			_get_rate("div_arm2"));

		clk_hw_get_rate(hws[CLK_DIV_ARM2]));

}

}

CLK_OF_DECLARE_DRIVER(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
 
CLK_OF_DECLARE_DRIVER(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);

drivers/clk/samsung/clk-exynos5420.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -1580,7 +1580,7 @@ static void __init exynos5x_clk_init(struct device_node *np, 
			ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),

			ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),

			ext_clk_match);

			ext_clk_match);





	if (_get_rate("fin_pll") == 24 * MHZ) {

	if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) {

		exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;

		exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;

		exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;

		exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;

		exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;

		exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;

drivers/clk/samsung/clk-s3c2410.c

+4 −2
Original line number Original line Diff line number Diff line
@@ -323,6 +323,7 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f, 
				    void __iomem *base)

				    void __iomem *base)

{

{

	struct samsung_clk_provider *ctx;

	struct samsung_clk_provider *ctx;

	struct clk_hw **hws;

	reg_base = base;

	reg_base = base;





	if (np) {

	if (np) {
@@ -332,13 +333,14 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f, 
	}

	}





	ctx = samsung_clk_init(np, reg_base, NR_CLKS);

	ctx = samsung_clk_init(np, reg_base, NR_CLKS);

	hws = ctx->clk_data.hws;





	/* Register external clocks only in non-dt cases */

	/* Register external clocks only in non-dt cases */

	if (!np)

	if (!np)

		s3c2410_common_clk_register_fixed_ext(ctx, xti_f);

		s3c2410_common_clk_register_fixed_ext(ctx, xti_f);





	if (current_soc == S3C2410) {

	if (current_soc == S3C2410) {

		if (_get_rate("xti") == 12 * MHZ) {

		if (clk_hw_get_rate(hws[XTI]) == 12 * MHZ) {

			s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl;

			s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl;

			s3c2410_plls[upll].rate_table = pll_s3c2410_12mhz_tbl;

			s3c2410_plls[upll].rate_table = pll_s3c2410_12mhz_tbl;

		}

		}
@@ -348,7 +350,7 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f, 
				ARRAY_SIZE(s3c2410_plls), reg_base);

				ARRAY_SIZE(s3c2410_plls), reg_base);





	} else { /* S3C2440, S3C2442 */

	} else { /* S3C2440, S3C2442 */

		if (_get_rate("xti") == 12 * MHZ) {

		if (clk_hw_get_rate(hws[XTI]) == 12 * MHZ) {

			/*

			/*

			 * plls follow different calculation schemes, with the

			 * plls follow different calculation schemes, with the

			 * upll following the same scheme as the s3c2410 plls

			 * upll following the same scheme as the s3c2410 plls

drivers/clk/samsung/clk-s3c64xx.c

+6 −2
Original line number Original line Diff line number Diff line
@@ -394,6 +394,7 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f, 
			     void __iomem *base)

			     void __iomem *base)

{

{

	struct samsung_clk_provider *ctx;

	struct samsung_clk_provider *ctx;

	struct clk_hw **hws;





	reg_base = base;

	reg_base = base;

	is_s3c6400 = s3c6400;

	is_s3c6400 = s3c6400;
@@ -405,6 +406,7 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f, 
	}

	}





	ctx = samsung_clk_init(np, reg_base, NR_CLKS);

	ctx = samsung_clk_init(np, reg_base, NR_CLKS);

	hws = ctx->clk_data.hws;





	/* Register external clocks. */

	/* Register external clocks. */

	if (!np)

	if (!np)
@@ -459,8 +461,10 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f, 
	pr_info("%s clocks: apll = %lu, mpll = %lu\n"

	pr_info("%s clocks: apll = %lu, mpll = %lu\n"

		"\tepll = %lu, arm_clk = %lu\n",

		"\tepll = %lu, arm_clk = %lu\n",

		is_s3c6400 ? "S3C6400" : "S3C6410",

		is_s3c6400 ? "S3C6400" : "S3C6410",

		_get_rate("fout_apll"),	_get_rate("fout_mpll"),

		clk_hw_get_rate(hws[MOUT_APLL]),

		_get_rate("fout_epll"), _get_rate("armclk"));

		clk_hw_get_rate(hws[MOUT_MPLL]),

		clk_hw_get_rate(hws[MOUT_EPLL]),

		clk_hw_get_rate(hws[ARMCLK]));

}

}





static void __init s3c6400_clk_init(struct device_node *np)

static void __init s3c6400_clk_init(struct device_node *np)