Commit 142439b0 authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer
Browse files

MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WAR 



Neither MIPS4K_ICACHE_REFILL_WAR nor MIPS_CACHE_SYNC_WAR are implemented,
so removing defines for it won't change anything.

Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 44def342

arch/mips/include/asm/mach-cavium-octeon/war.h

+0 −2
Original line number Diff line number Diff line
@@ -11,8 +11,6 @@ 


#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS4K_ICACHE_REFILL_WAR	0

#define MIPS_CACHE_SYNC_WAR		0

#define TX49XX_ICACHE_INDEX_INV_WAR	0

#define ICACHE_REFILLS_WORKAROUND_WAR	0

#define R10000_LLSC_WAR			0

arch/mips/include/asm/mach-generic/war.h

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Original line number Diff line number Diff line
@@ -10,8 +10,6 @@ 


#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS4K_ICACHE_REFILL_WAR	0

#define MIPS_CACHE_SYNC_WAR		0

#define TX49XX_ICACHE_INDEX_INV_WAR	0

#define ICACHE_REFILLS_WORKAROUND_WAR	0

#define R10000_LLSC_WAR			0

arch/mips/include/asm/mach-ip22/war.h

+0 −2
Original line number Diff line number Diff line
@@ -10,8 +10,6 @@ 


#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS4K_ICACHE_REFILL_WAR	0

#define MIPS_CACHE_SYNC_WAR		0

#define TX49XX_ICACHE_INDEX_INV_WAR	0

#define ICACHE_REFILLS_WORKAROUND_WAR	0

#define R10000_LLSC_WAR			0

arch/mips/include/asm/mach-ip27/war.h

+0 −2
Original line number Diff line number Diff line
@@ -10,8 +10,6 @@ 


#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS4K_ICACHE_REFILL_WAR	0

#define MIPS_CACHE_SYNC_WAR		0

#define TX49XX_ICACHE_INDEX_INV_WAR	0

#define ICACHE_REFILLS_WORKAROUND_WAR	0

#define R10000_LLSC_WAR			1

arch/mips/include/asm/mach-ip28/war.h

+0 −2
Original line number Diff line number Diff line
@@ -10,8 +10,6 @@ 


#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS4K_ICACHE_REFILL_WAR	0

#define MIPS_CACHE_SYNC_WAR		0

#define TX49XX_ICACHE_INDEX_INV_WAR	0

#define ICACHE_REFILLS_WORKAROUND_WAR	0

#define R10000_LLSC_WAR			1