Commit 44def342 authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer
Browse files

MIPS: Convert R4600_V2_HIT_CACHEOP into a config option 



Use a new config option to enable R4600 V2 cacheop hit workaround
and remove define from different war.h files.

Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 5e5b6527

arch/mips/Kconfig

+14 −0
Original line number Diff line number Diff line
@@ -640,6 +640,7 @@ config SGI_IP22 
	select SYS_SUPPORTS_BIG_ENDIAN

	select WAR_R4600_V1_INDEX_ICACHEOP

	select WAR_R4600_V1_HIT_CACHEOP

	select WAR_R4600_V2_HIT_CACHEOP

	select MIPS_L1_CACHE_SHIFT_7

	help

	  This are the SGI Indy, Challenge S and Indigo2, as well as certain
@@ -877,6 +878,7 @@ config SNI_RM 
	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_HIGHMEM

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select WAR_R4600_V2_HIT_CACHEOP

	help

	  The SNI RM200/300/400 are MIPS-based machines manufactured by

	  Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
@@ -2643,6 +2645,18 @@ config WAR_R4600_V1_INDEX_ICACHEOP 
config WAR_R4600_V1_HIT_CACHEOP

	bool



# Writeback and invalidate the primary cache dcache before DMA.

#

# R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,

# Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only

# operate correctly if the internal data cache refill buffer is empty.  These

# CACHE instructions should be separated from any potential data cache miss

# by a load instruction to an uncached address to empty the response buffer."

# (Revision 2.0 device errata from IDT available on https://www.idt.com/

# in .pdf format.)

config WAR_R4600_V2_HIT_CACHEOP

	bool



#

# - Highmem only makes sense for the 32-bit kernel.

# - The current highmem code will only work properly on physically indexed

arch/mips/include/asm/mach-cavium-octeon/war.h

+0 −1
Original line number Diff line number Diff line
@@ -9,7 +9,6 @@ 
#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H

#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H



#define R4600_V2_HIT_CACHEOP_WAR	0

#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS4K_ICACHE_REFILL_WAR	0

arch/mips/include/asm/mach-generic/war.h

+0 −1
Original line number Diff line number Diff line
@@ -8,7 +8,6 @@ 
#ifndef __ASM_MACH_GENERIC_WAR_H

#define __ASM_MACH_GENERIC_WAR_H



#define R4600_V2_HIT_CACHEOP_WAR	0

#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS4K_ICACHE_REFILL_WAR	0

arch/mips/include/asm/mach-ip22/war.h

+0 −5
Original line number Diff line number Diff line
@@ -8,11 +8,6 @@ 
#ifndef __ASM_MIPS_MACH_IP22_WAR_H

#define __ASM_MIPS_MACH_IP22_WAR_H



/*

 * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.

 */



#define R4600_V2_HIT_CACHEOP_WAR	1

#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS4K_ICACHE_REFILL_WAR	0

arch/mips/include/asm/mach-ip27/war.h

+0 −1
Original line number Diff line number Diff line
@@ -8,7 +8,6 @@ 
#ifndef __ASM_MIPS_MACH_IP27_WAR_H

#define __ASM_MIPS_MACH_IP27_WAR_H



#define R4600_V2_HIT_CACHEOP_WAR	0

#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS4K_ICACHE_REFILL_WAR	0