Commit 5e5b6527 authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer
Browse files

MIPS: Convert R4600_V1_HIT_CACHEOP into a config option 



Use a new config option to enable R4600 V1 cacheop hit workaround
and remove define from the different war.h files.

Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 802b8362

arch/mips/Kconfig

+28 −0
Original line number Diff line number Diff line
@@ -639,6 +639,7 @@ config SGI_IP22 
	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select WAR_R4600_V1_INDEX_ICACHEOP

	select WAR_R4600_V1_HIT_CACHEOP

	select MIPS_L1_CACHE_SHIFT_7

	help

	  This are the SGI Indy, Challenge S and Indigo2, as well as certain
@@ -2615,6 +2616,33 @@ config MIPS_CRC_SUPPORT 
config WAR_R4600_V1_INDEX_ICACHEOP

	bool



# Pleasures of the R4600 V1.x.  Cite from the IDT R4600 V1.7 errata:

#

#  18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,

#      Hit_Invalidate_D and Create_Dirty_Excl_D should only be

#      executed if there is no other dcache activity. If the dcache is

#      accessed for another instruction immeidately preceding when these

#      cache instructions are executing, it is possible that the dcache

#      tag match outputs used by these cache instructions will be

#      incorrect. These cache instructions should be preceded by at least

#      four instructions that are not any kind of load or store

#      instruction.

#

#      This is not allowed:    lw

#                              nop

#                              nop

#                              nop

#                              cache       Hit_Writeback_Invalidate_D

#

#      This is allowed:        lw

#                              nop

#                              nop

#                              nop

#                              nop

#                              cache       Hit_Writeback_Invalidate_D

config WAR_R4600_V1_HIT_CACHEOP

	bool



#

# - Highmem only makes sense for the 32-bit kernel.

# - The current highmem code will only work properly on physically indexed

arch/mips/include/asm/mach-cavium-octeon/war.h

+0 −1
Original line number Diff line number Diff line
@@ -9,7 +9,6 @@ 
#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H

#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H



#define R4600_V1_HIT_CACHEOP_WAR	0

#define R4600_V2_HIT_CACHEOP_WAR	0

#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

arch/mips/include/asm/mach-generic/war.h

+0 −1
Original line number Diff line number Diff line
@@ -8,7 +8,6 @@ 
#ifndef __ASM_MACH_GENERIC_WAR_H

#define __ASM_MACH_GENERIC_WAR_H



#define R4600_V1_HIT_CACHEOP_WAR	0

#define R4600_V2_HIT_CACHEOP_WAR	0

#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

arch/mips/include/asm/mach-ip22/war.h

+0 −1
Original line number Diff line number Diff line
@@ -12,7 +12,6 @@ 
 * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.

 */



#define R4600_V1_HIT_CACHEOP_WAR	1

#define R4600_V2_HIT_CACHEOP_WAR	1

#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

arch/mips/include/asm/mach-ip27/war.h

+0 −1
Original line number Diff line number Diff line
@@ -8,7 +8,6 @@ 
#ifndef __ASM_MIPS_MACH_IP27_WAR_H

#define __ASM_MIPS_MACH_IP27_WAR_H



#define R4600_V1_HIT_CACHEOP_WAR	0

#define R4600_V2_HIT_CACHEOP_WAR	0

#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0