Commit 143dfcca authored by Abhinav Kumar's avatar Abhinav Kumar Committed by Dmitry Baryshkov
Browse files

drm/msm/dpu: rename enable_compression() to program_intf_cmd_cfg() 



Rename the intf's enable_compression() op to program_intf_cmd_cfg()
and allow it to accept a struct intf_cmd_mode_cfg to program
all the bits at once. This can be re-used by widebus later on as
well as it touches the same register.

changes in v5:
	- rename struct intf_cmd_mode_cfg to dpu_hw_intf_cmd_mode_cfg
	- remove couple of comments

Signed-off-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/546806/
Link: https://lore.kernel.org/r/20230712012003.2212-5-quic_abhinavk@quicinc.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 4c6df9a4

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

+6 −2
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( 
			to_dpu_encoder_phys_cmd(phys_enc);

	struct dpu_hw_ctl *ctl;

	struct dpu_hw_intf_cfg intf_cfg = { 0 };

	struct dpu_hw_intf_cmd_mode_cfg cmd_mode_cfg = {};



	ctl = phys_enc->hw_ctl;

	if (!ctl->ops.setup_intf_cfg)
@@ -68,8 +69,11 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( 
				phys_enc->hw_intf,

				phys_enc->hw_pp->idx);



	if (intf_cfg.dsc != 0 && phys_enc->hw_intf->ops.enable_compression)

		phys_enc->hw_intf->ops.enable_compression(phys_enc->hw_intf);

	if (intf_cfg.dsc != 0)

		cmd_mode_cfg.data_compress = true;



	if (phys_enc->hw_intf->ops.program_intf_cmd_cfg)

		phys_enc->hw_intf->ops.program_intf_cmd_cfg(phys_enc->hw_intf, &cmd_mode_cfg);

}



static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

+5 −3
Original line number Diff line number Diff line
@@ -513,10 +513,12 @@ static void dpu_hw_intf_disable_autorefresh(struct dpu_hw_intf *intf, 


}



static void dpu_hw_intf_enable_compression(struct dpu_hw_intf *ctx)

static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx,

					     struct dpu_hw_intf_cmd_mode_cfg *cmd_mode_cfg)

{

	u32 intf_cfg2 = DPU_REG_READ(&ctx->hw, INTF_CONFIG2);



	if (cmd_mode_cfg->data_compress)

		intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;



	DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2);
@@ -544,7 +546,7 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, 
	}



	if (mdss_rev->core_major_ver >= 7)

		ops->enable_compression = dpu_hw_intf_enable_compression;

		ops->program_intf_cmd_cfg = dpu_hw_intf_program_intf_cmd_cfg;

}



struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h

+7 −2
Original line number Diff line number Diff line
@@ -48,6 +48,10 @@ struct dpu_hw_intf_status { 
	u32 line_count;		/* current line count including blanking */

};



struct dpu_hw_intf_cmd_mode_cfg {

	u8 data_compress;	/* enable data compress between dpu and dsi */

};



/**

 * struct dpu_hw_intf_ops : Interface to the interface Hw driver functions

 *  Assumption is these functions will be called after clocks are enabled
@@ -70,7 +74,7 @@ struct dpu_hw_intf_status { 
 * @get_autorefresh:            Retrieve autorefresh config from hardware

 *                              Return: 0 on success, -ETIMEDOUT on timeout

 * @vsync_sel:                  Select vsync signal for tear-effect configuration

 * @enable_compression:         Enable data compression

 * @program_intf_cmd_cfg:       Program the DPU to interface datapath for command mode

 */

struct dpu_hw_intf_ops {

	void (*setup_timing_gen)(struct dpu_hw_intf *intf,
@@ -108,7 +112,8 @@ struct dpu_hw_intf_ops { 
	 */

	void (*disable_autorefresh)(struct dpu_hw_intf *intf, uint32_t encoder_id, u16 vdisplay);



	void (*enable_compression)(struct dpu_hw_intf *intf);

	void (*program_intf_cmd_cfg)(struct dpu_hw_intf *intf,

				     struct dpu_hw_intf_cmd_mode_cfg *cmd_mode_cfg);

};



struct dpu_hw_intf {