Commit 1a9629f7 authored by Marek Vasut's avatar Marek Vasut Committed by Shawn Guo
Browse files

arm64: dts: imx8mq: Deduplicate PCIe clock-names property 



Move the PCIe clock-names property from various DTs into SoC dtsi to
reduce duplication. In case of a couple of boards, reorder the clock
so they match the order in yaml DT bindings.

Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mq.dtsi, imx8mq-tqma8mq-mba8mx.dts
Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Reviewed-by: default avatarRichard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 3c033fb1

arch/arm64/boot/dts/freescale/imx8mq-evk.dts

+4 −6
Original line number Diff line number Diff line
@@ -356,10 +356,9 @@ &pcie0 { 
	pinctrl-0 = <&pinctrl_pcie0>;

	reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;

	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,

		 <&clk IMX8MQ_CLK_PCIE1_AUX>,

		 <&pcie0_refclk>,

		 <&clk IMX8MQ_CLK_PCIE1_PHY>,

		 <&pcie0_refclk>;

	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";

		 <&clk IMX8MQ_CLK_PCIE1_AUX>;

	vph-supply = <&vgen5_reg>;

	status = "okay";

};
@@ -369,10 +368,9 @@ &pcie1 { 
	pinctrl-0 = <&pinctrl_pcie1>;

	reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;

	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,

		 <&clk IMX8MQ_CLK_PCIE2_AUX>,

		 <&pcie0_refclk>,

		 <&clk IMX8MQ_CLK_PCIE2_PHY>,

		 <&pcie0_refclk>;

	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";

		 <&clk IMX8MQ_CLK_PCIE2_AUX>;

	vpcie-supply = <&reg_pcie1>;

	vph-supply = <&vgen5_reg>;

	status = "okay";

arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts

+4 −6
Original line number Diff line number Diff line
@@ -245,20 +245,18 @@ &pcie0 { 
	pinctrl-0 = <&pinctrl_pcie0>;

	reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;

	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,

		 <&clk IMX8MQ_CLK_PCIE1_AUX>,

		 <&pcie0_refclk>,

		 <&clk IMX8MQ_CLK_PCIE1_PHY>,

		 <&pcie0_refclk>;

	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";

		 <&clk IMX8MQ_CLK_PCIE1_AUX>;

	status = "okay";

};



/* Intel Ethernet Controller I210/I211 */

&pcie1 {

	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,

		 <&clk IMX8MQ_CLK_PCIE2_AUX>,

		 <&pcie1_refclk>,

		 <&clk IMX8MQ_CLK_PCIE2_PHY>,

		 <&pcie1_refclk>;

	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";

		 <&clk IMX8MQ_CLK_PCIE2_AUX>;

	fsl,max-link-speed = <1>;

	status = "okay";

};

arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts

+2 −3
Original line number Diff line number Diff line
@@ -197,10 +197,9 @@ &pcie1 { 
	pinctrl-0 = <&pinctrl_pcie1>;

	reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;

	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,

		 <&clk IMX8MQ_CLK_PCIE2_AUX>,

		 <&pcie1_refclk>,

		 <&clk IMX8MQ_CLK_PCIE2_PHY>,

		 <&pcie1_refclk>;

	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";

		 <&clk IMX8MQ_CLK_PCIE2_AUX>;

	status = "okay";

};

arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts

+4 −6
Original line number Diff line number Diff line
@@ -105,10 +105,9 @@ &led2 { 
&pcie0 {

	reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;

	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,

		 <&clk IMX8MQ_CLK_PCIE1_AUX>,

		 <&pcie0_refclk>,

		 <&clk IMX8MQ_CLK_PCIE1_PHY>,

		 <&pcie0_refclk>;

	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";

		 <&clk IMX8MQ_CLK_PCIE1_AUX>;

	epdev_on-supply = <&reg_vcc_3v3>;

	hard-wired = <1>;

	status = "okay";
@@ -120,10 +119,9 @@ &pcie0 { 
 */

&pcie1 {

	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,

		 <&clk IMX8MQ_CLK_PCIE2_AUX>,

		 <&pcie1_refclk>,

		 <&clk IMX8MQ_CLK_PCIE2_PHY>,

		 <&pcie1_refclk>;

	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";

		 <&clk IMX8MQ_CLK_PCIE2_AUX>;

	epdev_on-supply = <&reg_vcc_3v3>;

	hard-wired = <1>;

	status = "okay";

arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi

+4 −6
Original line number Diff line number Diff line
@@ -551,10 +551,9 @@ &pcie0 { 
	pinctrl-0 = <&pinctrl_pcie0>;

	reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;

	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,

	         <&clk IMX8MQ_CLK_PCIE1_AUX>,

	         <&pcie0_refclk>,

	         <&clk IMX8MQ_CLK_PCIE1_PHY>,

	         <&pcie0_refclk>;

	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";

	         <&clk IMX8MQ_CLK_PCIE1_AUX>;

	vph-supply = <&vgen5_reg>;

	status = "okay";

};
@@ -564,10 +563,9 @@ &pcie1 { 
	pinctrl-0 = <&pinctrl_pcie1>;

	reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;

	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,

	         <&clk IMX8MQ_CLK_PCIE2_AUX>,

	         <&pcie1_refclk>,

	         <&clk IMX8MQ_CLK_PCIE2_PHY>,

	         <&pcie1_refclk>;

	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";

	         <&clk IMX8MQ_CLK_PCIE2_AUX>;

	vph-supply = <&vgen5_reg>;

	status = "okay";

};