Skip to content
Commit 2110add8 authored by Xingyu Wu's avatar Xingyu Wu Committed by Conor Dooley
Browse files

dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs



Add PLL clock inputs from PLL clock generator.

Reviewed-by: default avatarEmil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarXingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent c81f7845
Loading
Loading
Loading
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please to comment