Commit 23737b95 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
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arm64: dts: qcom: sm6350: Add USB1 nodes 



Add nodes required for USB1 to function. SM6350 (thankfully) resuses SDM845 and
SC7180 IP, so no additional code porting is required.

Acked-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
[bjorn: Renamed dwc3 node "usb"]
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923162204.21752-7-konrad.dybcio@somainline.org
parent 538f4bcd

arch/arm64/boot/dts/qcom/sm6350.dtsi

+101 −0
Original line number Diff line number Diff line
@@ -388,12 +388,113 @@ tcsr_mutex: hwlock@1f40000 { 
			#hwlock-cells = <1>;

		};



		usb_1_hsphy: phy@88e3000 {

			compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy";

			reg = <0 0x088e3000 0 0x400>;

			status = "disabled";

			#phy-cells = <0>;



			clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>;

			clock-names = "cfg_ahb", "ref";



			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

		};



		usb_1_qmpphy: phy@88e9000 {

			compatible = "qcom,sc7180-qmp-usb3-dp-phy";

			reg = <0 0x088e9000 0 0x200>,

			      <0 0x088e8000 0 0x40>,

			      <0 0x088ea000 0 0x200>;

			status = "disabled";

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;



			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,

				 <&rpmhcc RPMH_QLINK_CLK>,

				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,

				 <&xo_board>;

			clock-names = "aux", "ref", "com_aux", "cfg_ahb";



			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,

				 <&gcc GCC_USB3_PHY_PRIM_BCR>;

			reset-names = "phy", "common";



			usb_1_ssphy: usb3-phy@88e9200 {

				reg = <0 0x088e9200 0 0x200>,

				      <0 0x088e9400 0 0x200>,

				      <0 0x088e9c00 0 0x400>,

				      <0 0x088e9600 0 0x200>,

				      <0 0x088e9800 0 0x200>,

				      <0 0x088e9a00 0 0x100>;

				#clock-cells = <0>;

				#phy-cells = <0>;

				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;

				clock-names = "pipe0";

				clock-output-names = "usb3_phy_pipe_clk_src";

			};



			dp_phy: dp-phy@88ea200 {

				reg = <0 0x088ea200 0 0x200>,

				      <0 0x088ea400 0 0x200>,

				      <0 0x088eac00 0 0x400>,

				      <0 0x088ea600 0 0x200>,

				      <0 0x088ea800 0 0x200>,

				      <0 0x088eaa00 0 0x100>;

				#phy-cells = <0>;

				#clock-cells = <1>;

				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;

				clock-names = "pipe0";

				clock-output-names = "usb3_phy_pipe_clk_src";

			};

		};



		system-cache-controller@9200000 {

			compatible = "qcom,sm6350-llcc";

			reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;

			reg-names = "llcc_base", "llcc_broadcast_base";

		};



		usb_1: usb@a6f8800 {

			compatible = "qcom,sm6350-dwc3", "qcom,dwc3";

			reg = <0 0x0a6f8800 0 0x400>;

			status = "disabled";

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;



			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,

				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,

				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,

				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,

				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;

			clock-names = "cfg_noc", "core", "iface", "mock_utmi",

				      "sleep";



			interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,

					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,

					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,

					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",

					  "dm_hs_phy_irq", "ss_phy_irq";



			power-domains = <&gcc USB30_PRIM_GDSC>;



			resets = <&gcc GCC_USB30_PRIM_BCR>;



			usb_1_dwc3: usb@a600000 {

				compatible = "snps,dwc3";

				reg = <0 0x0a600000 0 0xcd00>;

				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;

				snps,dis_u2_susphy_quirk;

				snps,dis_enblslpm_quirk;

				snps,has-lpm-erratum;

				snps,hird-threshold = /bits/ 8 <0x10>;

				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;

				phy-names = "usb2-phy", "usb3-phy";

			};

		};



		pdc: interrupt-controller@b220000 {

			compatible = "qcom,sm6350-pdc", "qcom,pdc";

			reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;