Commit 23dbafd8 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

pinctrl: renesas: r8a77980: Optimize fixed-width reserved fields 



Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 198 bytes.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/0bf6b069a794b3c56c0c9311ac4b2ada577a9cb7.1649865241.git.geert+renesas@glider.be
parent 37362c77

drivers/pinctrl/renesas/pfc-r8a77980.c

+28 −63
Original line number Diff line number Diff line
@@ -278,9 +278,6 @@ 
#define IP10_11_8	FM(FSO_CFE_0_N)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA22)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP10_15_12	FM(FSO_CFE_1_N)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA23)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP10_19_16	FM(FSO_TOE_N)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP10_23_20	F_(0, 0)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP10_27_24	F_(0, 0)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP10_31_28	F_(0, 0)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)



#define PINMUX_GPSR	\

\
@@ -340,9 +337,9 @@ FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 \ 
FM(IP8_11_8)	IP8_11_8	FM(IP9_11_8)	IP9_11_8	FM(IP10_11_8)	IP10_11_8 \

FM(IP8_15_12)	IP8_15_12	FM(IP9_15_12)	IP9_15_12	FM(IP10_15_12)	IP10_15_12 \

FM(IP8_19_16)	IP8_19_16	FM(IP9_19_16)	IP9_19_16	FM(IP10_19_16)	IP10_19_16 \

FM(IP8_23_20)	IP8_23_20	FM(IP9_23_20)	IP9_23_20	FM(IP10_23_20)	IP10_23_20 \

FM(IP8_27_24)	IP8_27_24	FM(IP9_27_24)	IP9_27_24	FM(IP10_27_24)	IP10_27_24 \

FM(IP8_31_28)	IP8_31_28	FM(IP9_31_28)	IP9_31_28	FM(IP10_31_28)	IP10_31_28

FM(IP8_23_20)	IP8_23_20	FM(IP9_23_20)	IP9_23_20 \

FM(IP8_27_24)	IP8_27_24	FM(IP9_27_24)	IP9_27_24 \

FM(IP8_31_28)	IP8_31_28	FM(IP9_31_28)	IP9_31_28



/* MOD_SEL0 */		/* 0 */			/* 1 */

#define MOD_SEL0_11	FM(SEL_CANFD0_0)	FM(SEL_CANFD0_1)
@@ -2507,17 +2504,11 @@ static const struct sh_pfc_function pinmux_functions[] = { 
static const struct pinmux_cfg_reg pinmux_config_regs[] = {

#define F_(x, y)	FN_##y

#define FM(x)		FN_##x

	{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,

			     GROUP(-10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),

			     GROUP(

		/* GP0_31_22 RESERVED */

		GP_0_21_FN,	GPSR0_21,

		GP_0_20_FN,	GPSR0_20,

		GP_0_19_FN,	GPSR0_19,
@@ -2609,22 +2600,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_2_1_FN,	GPSR2_1,

		GP_2_0_FN,	GPSR2_0, ))

	},

	{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,

			     GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1),

			     GROUP(

		/* GP3_31_17 RESERVED */

		GP_3_16_FN,	GPSR3_16,

		GP_3_15_FN,	GPSR3_15,

		GP_3_14_FN,	GPSR3_14,
@@ -2643,14 +2623,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_3_1_FN,	GPSR3_1,

		GP_3_0_FN,	GPSR3_0, ))

	},

	{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,

			     GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1),

			     GROUP(

		/* GP4_31_25 RESERVED */

		GP_4_24_FN,	GPSR4_24,

		GP_4_23_FN,	GPSR4_23,

		GP_4_22_FN,	GPSR4_22,
@@ -2677,24 +2655,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_4_1_FN,	GPSR4_1,

		GP_4_0_FN,	GPSR4_0, ))

	},

	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,

			     GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1),

			     GROUP(

		/* GP5_31_15 RESERVED */

		GP_5_14_FN,	GPSR5_14,

		GP_5_13_FN,	GPSR5_13,

		GP_5_12_FN,	GPSR5_12,
@@ -2816,10 +2781,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		IP9_7_4

		IP9_3_0 ))

	},

	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(

		IP10_31_28

		IP10_27_24

		IP10_23_20

	{ PINMUX_CFG_REG_VAR("IPSR10", 0xe6060228, 32,

			     GROUP(-12, 4, 4, 4, 4, 4),

			     GROUP(

		/* IP10_31_20 RESERVED */

		IP10_19_16

		IP10_15_12

		IP10_11_8