Commit 24a1c023 authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer
Browse files

MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config option 



Use a new config option to enable TX49XX I-cache index invalidate
workaround and remove define from different war.h files.

Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 142439b0

arch/mips/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -890,6 +890,7 @@ config MACH_TX39XX 


config MACH_TX49XX

	bool "Toshiba TX49 series based machines"

	select WAR_TX49XX_ICACHE_INDEX_INV



config MIKROTIK_RB532

	bool "Mikrotik RB532 boards"
@@ -2657,6 +2658,14 @@ config WAR_R4600_V1_HIT_CACHEOP 
config WAR_R4600_V2_HIT_CACHEOP

	bool



# From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for

# the line which this instruction itself exists, the following

# operation is not guaranteed."

#

# Workaround: do two phase flushing for Index_Invalidate_I

config WAR_TX49XX_ICACHE_INDEX_INV

	bool



#

# - Highmem only makes sense for the 32-bit kernel.

# - The current highmem code will only work properly on physically indexed

arch/mips/include/asm/mach-cavium-octeon/war.h

+0 −1
Original line number Diff line number Diff line
@@ -11,7 +11,6 @@ 


#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define TX49XX_ICACHE_INDEX_INV_WAR	0

#define ICACHE_REFILLS_WORKAROUND_WAR	0

#define R10000_LLSC_WAR			0

#define MIPS34K_MISSED_ITLB_WAR		0

arch/mips/include/asm/mach-generic/war.h

+0 −1
Original line number Diff line number Diff line
@@ -10,7 +10,6 @@ 


#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define TX49XX_ICACHE_INDEX_INV_WAR	0

#define ICACHE_REFILLS_WORKAROUND_WAR	0

#define R10000_LLSC_WAR			0

#define MIPS34K_MISSED_ITLB_WAR		0

arch/mips/include/asm/mach-ip22/war.h

+0 −1
Original line number Diff line number Diff line
@@ -10,7 +10,6 @@ 


#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define TX49XX_ICACHE_INDEX_INV_WAR	0

#define ICACHE_REFILLS_WORKAROUND_WAR	0

#define R10000_LLSC_WAR			0

#define MIPS34K_MISSED_ITLB_WAR		0

arch/mips/include/asm/mach-ip27/war.h

+0 −1
Original line number Diff line number Diff line
@@ -10,7 +10,6 @@ 


#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define TX49XX_ICACHE_INDEX_INV_WAR	0

#define ICACHE_REFILLS_WORKAROUND_WAR	0

#define R10000_LLSC_WAR			1

#define MIPS34K_MISSED_ITLB_WAR		0