Commit 256ec489 authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer
Browse files

MIPS: Convert R10000_LLSC_WAR info a config option 



Use a new config option to enabel R1000_LLSC workaound and remove
define from different war.h files.

Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 886ee136

arch/mips/Kconfig

+8 −0
Original line number Diff line number Diff line
@@ -669,6 +669,7 @@ config SGI_IP27 
	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_NUMA

	select SYS_SUPPORTS_SMP

	select WAR_R10000_LLSC

	select MIPS_L1_CACHE_SHIFT_7

	select NUMA

	help
@@ -704,6 +705,7 @@ config SGI_IP28 
	select SYS_HAS_EARLY_PRINTK

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select WAR_R10000_LLSC

	select MIPS_L1_CACHE_SHIFT_7

	help

	  This is the SGI Indigo2 with R10000 processor.  To compile a Linux
@@ -730,6 +732,7 @@ config SGI_IP30 
	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_SMP

	select WAR_R10000_LLSC

	select MIPS_L1_CACHE_SHIFT_7

	select ARC_MEMORY

	help
@@ -2675,6 +2678,11 @@ config WAR_TX49XX_ICACHE_INDEX_INV 
config WAR_ICACHE_REFILLS

	bool



# On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that

# may cause ll / sc and lld / scd sequences to execute non-atomically.

config WAR_R10000_LLSC

	bool



#

# - Highmem only makes sense for the 32-bit kernel.

# - The current highmem code will only work properly on physically indexed

arch/mips/include/asm/futex.h

+2 −2
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ 


#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)		\

{									\

	if (cpu_has_llsc && R10000_LLSC_WAR) {				\

	if (cpu_has_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {	\

		__asm__ __volatile__(					\

		"	.set	push				\n"	\

		"	.set	noat				\n"	\
@@ -133,7 +133,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, 
	if (!access_ok(uaddr, sizeof(u32)))

		return -EFAULT;



	if (cpu_has_llsc && R10000_LLSC_WAR) {

	if (cpu_has_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {

		__asm__ __volatile__(

		"# futex_atomic_cmpxchg_inatomic			\n"

		"	.set	push					\n"

arch/mips/include/asm/llsc.h

+1 −1
Original line number Diff line number Diff line
@@ -28,7 +28,7 @@ 
 * works around a bug present in R10000 CPUs prior to revision 3.0 that could

 * cause ll-sc sequences to execute non-atomically.

 */

#if R10000_LLSC_WAR

#ifdef CONFIG_WAR_R10000_LLSC

# define __SC_BEQZ "beqzl	"

#elif MIPS_ISA_REV >= 6

# define __SC_BEQZ "beqzc	"

arch/mips/include/asm/local.h

+2 −2
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ static __inline__ long local_add_return(long i, local_t * l) 
{

	unsigned long result;



	if (kernel_uses_llsc && R10000_LLSC_WAR) {

	if (kernel_uses_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {

		unsigned long temp;



		__asm__ __volatile__(
@@ -80,7 +80,7 @@ static __inline__ long local_sub_return(long i, local_t * l) 
{

	unsigned long result;



	if (kernel_uses_llsc && R10000_LLSC_WAR) {

	if (kernel_uses_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {

		unsigned long temp;



		__asm__ __volatile__(

arch/mips/include/asm/mach-cavium-octeon/war.h

+0 −1
Original line number Diff line number Diff line
@@ -11,7 +11,6 @@ 


#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define R10000_LLSC_WAR			0

#define MIPS34K_MISSED_ITLB_WAR		0



#define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR	\