Commit 886ee136 authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer
Browse files

MIPS: Convert ICACHE_REFILLS_WORKAROUND_WAR into a config option 



Use a new config option to enable I-cache refill workaround and remove
define from different war.h files.

Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 24a1c023

arch/mips/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -568,6 +568,7 @@ config MIPS_MALTA 
	select SYS_SUPPORTS_VPE_LOADER

	select SYS_SUPPORTS_ZBOOT

	select USE_OF

	select WAR_ICACHE_REFILLS

	select ZONE_DMA32 if 64BIT

	help

	  This enables support for the MIPS Technologies Malta evaluation
@@ -756,6 +757,7 @@ config SGI_IP32 
	select SYS_HAS_CPU_NEVADA

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select WAR_ICACHE_REFILLS

	help

	  If you want this kernel to run on SGI O2 workstation, say Y here.
@@ -2666,6 +2668,13 @@ config WAR_R4600_V2_HIT_CACHEOP 
config WAR_TX49XX_ICACHE_INDEX_INV

	bool



# The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra

# opposes it being called that) where invalid instructions in the same

# I-cache line worth of instructions being fetched may case spurious

# exceptions.

config WAR_ICACHE_REFILLS

	bool



#

# - Highmem only makes sense for the 32-bit kernel.

# - The current highmem code will only work properly on physically indexed

arch/mips/include/asm/mach-cavium-octeon/war.h

+0 −1
Original line number Diff line number Diff line
@@ -11,7 +11,6 @@ 


#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define ICACHE_REFILLS_WORKAROUND_WAR	0

#define R10000_LLSC_WAR			0

#define MIPS34K_MISSED_ITLB_WAR		0

arch/mips/include/asm/mach-generic/war.h

+0 −1
Original line number Diff line number Diff line
@@ -10,7 +10,6 @@ 


#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define ICACHE_REFILLS_WORKAROUND_WAR	0

#define R10000_LLSC_WAR			0

#define MIPS34K_MISSED_ITLB_WAR		0

arch/mips/include/asm/mach-ip22/war.h

+0 −1
Original line number Diff line number Diff line
@@ -10,7 +10,6 @@ 


#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define ICACHE_REFILLS_WORKAROUND_WAR	0

#define R10000_LLSC_WAR			0

#define MIPS34K_MISSED_ITLB_WAR		0

arch/mips/include/asm/mach-ip27/war.h

+0 −1
Original line number Diff line number Diff line
@@ -10,7 +10,6 @@ 


#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define ICACHE_REFILLS_WORKAROUND_WAR	0

#define R10000_LLSC_WAR			1

#define MIPS34K_MISSED_ITLB_WAR		0