drm/amdgpu/mes: correct register offset for sienna_cichlid

Correct CP_MES_IC_OP_CNTL register address for sienna_cichlid on mes v10.1.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>