Commit 291f63e7 authored by Caz Yokoyama's avatar Caz Yokoyama Committed by José Roberto de Souza
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drm/i915/display/adlp: Adjust MBUS DBOX BW and B credits 



Alderlake-P has different MBUS DBOX BW and B credits than other
platforms, so here setting it properly.

BSpec: 49213
BSpec: 50343
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarCaz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220330155724.255226-2-jose.souza@intel.com
parent d7ade5f2

drivers/gpu/drm/i915/display/intel_display.c

+4 −1
Original line number Diff line number Diff line
@@ -1845,7 +1845,10 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus) 
	else

		val |= MBUS_DBOX_A_CREDIT(2);



	if (DISPLAY_VER(dev_priv) >= 12) {

	if (IS_ALDERLAKE_P(dev_priv)) {

		val |= MBUS_DBOX_BW_CREDIT(2);

		val |= MBUS_DBOX_B_CREDIT(8);

	} else if (DISPLAY_VER(dev_priv) >= 12) {

		val |= MBUS_DBOX_BW_CREDIT(2);

		val |= MBUS_DBOX_B_CREDIT(12);

	} else {