Commit 31354121 authored by Dinh Nguyen's avatar Dinh Nguyen
Browse files

arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node 



The sdmmc controller's CIU(Card Interface Unit) clock's phase can be
adjusted through the register in the system manager. Add the binding
"altr,sysmgr-syscon" to the SDMMC node for the driver to access the
system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to
designate the smpsel and drvsel properties for the CIU clock.

Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
parent 3b500ff3

arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -309,6 +309,7 @@ mmc: mmc@ff808000 { 
				 <&clkmgr STRATIX10_SDMMC_CLK>;

			clock-names = "biu", "ciu";

			iommus = <&smmu 5>;

			altr,sysmgr-syscon = <&sysmgr 0x28 4>;

			status = "disabled";

		};

arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts

+1 −0
Original line number Diff line number Diff line
@@ -105,6 +105,7 @@ &mmc { 
	cap-mmc-highspeed;

	broken-cd;

	bus-width = <4>;

	clk-phase-sd-hs = <0>, <135>;

};



&osc1 {

arch/arm64/boot/dts/intel/socfpga_agilex.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -313,6 +313,7 @@ mmc: mmc@ff808000 { 
				 <&clkmgr AGILEX_SDMMC_CLK>;

			clock-names = "biu", "ciu";

			iommus = <&smmu 5>;

			altr,sysmgr-syscon = <&sysmgr 0x28 4>;

			status = "disabled";

		};

arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts

+1 −0
Original line number Diff line number Diff line
@@ -83,6 +83,7 @@ &mmc { 
	cap-sd-highspeed;

	broken-cd;

	bus-width = <4>;

	clk-phase-sd-hs = <0>, <135>;

};



&osc1 {

arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts

+1 −0
Original line number Diff line number Diff line
@@ -74,6 +74,7 @@ &mmc { 
	cap-sd-highspeed;

	broken-cd;

	bus-width = <4>;

	clk-phase-sd-hs = <0>, <135>;

};



&osc1 {