Commit 3b500ff3 authored by Dinh Nguyen's avatar Dinh Nguyen
Browse files

arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node 



The sdmmc controller's CIU(Card Interface Unit) clock's phase can be
adjusted through the register in the system manager. Add the binding
"altr,sysmgr-syscon" to the SDMMC node for the driver to access the
system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to
designate the smpsel and drvsel properties for the CIU clock.

Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
parent 63fb606a

arch/arm/boot/dts/socfpga.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -764,6 +764,7 @@ mmc: mmc@ff704000 { 
			clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;

			clock-names = "biu", "ciu";

			resets = <&rst SDMMC_RESET>;

			altr,sysmgr-syscon = <&sysmgr 0x108 3>;

			status = "disabled";

		};

arch/arm/boot/dts/socfpga_arria10.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -665,6 +665,7 @@ mmc: mmc@ff808000 { 
			clocks = <&l4_mp_clk>, <&sdmmc_clk>;

			clock-names = "biu", "ciu";

			resets = <&rst SDMMC_RESET>;

			altr,sysmgr-syscon = <&sysmgr 0x28 4>;

			status = "disabled";

		};

arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -73,6 +73,7 @@ &mmc { 
	cap-sd-highspeed;

	broken-cd;

	bus-width = <4>;

	clk-phase-sd-hs = <0>, <135>;

};



&osc1 {

arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts

+1 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ &mmc { 
	cap-mmc-highspeed;

	broken-cd;

	bus-width = <4>;

	clk-phase-sd-hs = <0>, <135>;

};



&eccmgr {

arch/arm/boot/dts/socfpga_arria5.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ mmc0: mmc@ff704000 { 
			bus-width = <4>;

			cap-mmc-highspeed;

			cap-sd-highspeed;

			clk-phase-sd-hs = <0>, <135>;

		};



		sysmgr@ffd08000 {