Commit 315e2d8a authored by Erwan Le Ray's avatar Erwan Le Ray Committed by Greg Kroah-Hartman
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serial: stm32: fix FIFO flush in startup and set_termios 



Fifo flush set USART_RQR register by calling stm32_usart_set_bits
routine (Read/Modify/Write). USART_RQR register is a write only
register. So, read before write isn't correct / relevant to flush
the FIFOs.
Replace stm32_usart_set_bits call by writel_relaxed.

Fixes: 84872dc4 ("serial: stm32: add RX and TX FIFO flush")
Signed-off-by: default avatarErwan Le Ray <erwan.leray@foss.st.com>
Link: https://lore.kernel.org/r/20210304162308.8984-11-erwan.leray@foss.st.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent f16b90c2

drivers/tty/serial/stm32-usart.c

+3 −3
Original line number Diff line number Diff line
@@ -657,7 +657,7 @@ static int stm32_usart_startup(struct uart_port *port) 


	/* RX FIFO Flush */

	if (ofs->rqr != UNDEF_REG)

		stm32_usart_set_bits(port, ofs->rqr, USART_RQR_RXFRQ);

		writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr);



	/* RX enabling */

	val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit);
@@ -762,8 +762,8 @@ static void stm32_usart_set_termios(struct uart_port *port, 


	/* flush RX & TX FIFO */

	if (ofs->rqr != UNDEF_REG)

		stm32_usart_set_bits(port, ofs->rqr,

				     USART_RQR_TXFRQ | USART_RQR_RXFRQ);

		writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,

			       port->membase + ofs->rqr);



	cr1 = USART_CR1_TE | USART_CR1_RE;

	if (stm32_port->fifoen)