Commit 3896b8f0 authored Jul 04, 2022 by Geert Uytterhoeven

arm64: dts: renesas: spider-cpu: Fix scif0/scif3 sort order

The scif0 nodes were accidentally inserted after the scif3 nodes,
breaking alphabetical sort order.

Fixes: 1614c862 ("arm64: dts: renesas: spider-cpu: Enable SCIF0 on second connector")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/2fe0e782351c202ed009dcd658f4bceec8f3a56d.1656951240.git.geert+renesas@glider.be

parent 5b6d7c3c

arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi

+9 −9

Original line number	Diff line number	Diff line
		@@ -55,16 +55,16 @@ i2c4_pins: i2c4 {
		function = "i2c4";
		};

		scif3_pins: scif3 {
		groups = "scif3_data", "scif3_ctrl";
		function = "scif3";
		};

		scif0_pins: scif0 {
		groups = "scif0_data", "scif0_ctrl";
		function = "scif0";
		};

		scif3_pins: scif3 {
		groups = "scif3_data", "scif3_ctrl";
		function = "scif3";
		};

		scif_clk_pins: scif_clk {
		groups = "scif_clk";
		function = "scif_clk";
		@@ -76,16 +76,16 @@ &rwdt {
		status = "okay";
		};

		&scif3 {
		pinctrl-0 = <&scif3_pins>;
		&scif0 {
		pinctrl-0 = <&scif0_pins>;
		pinctrl-names = "default";

		uart-has-rtscts;
		status = "okay";
		};

		&scif0 {
		pinctrl-0 = <&scif0_pins>;
		&scif3 {
		pinctrl-0 = <&scif3_pins>;
		pinctrl-names = "default";

		uart-has-rtscts;