Commit 3a87e25a authored by Daniel Miess's avatar Daniel Miess Committed by Alex Deucher
Browse files

drm/amd/display: Fix DP2 link training failure with RCO 



[Why]
When RCO is enabled for symclk32_le we get failures during
DP2 link traing compliance tests.

[How]
Break out symclk32_le RCO into a separate function that is
called for hpo when link is enabled/disabled.

Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: default avatarAlan Liu <haoping.liu@amd.com>
Signed-off-by: default avatarDaniel Miess <daniel.miess@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2ad127ba

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c

+29 −20
Original line number Diff line number Diff line
@@ -284,19 +284,11 @@ void dccg31_enable_symclk32_le( 
	/* select one of the PHYD32CLKs as the source for symclk32_le */

	switch (hpo_le_inst) {

	case 0:

		if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

			REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,

					SYMCLK32_LE0_GATE_DISABLE, 1,

					SYMCLK32_ROOT_LE0_GATE_DISABLE, 1);

		REG_UPDATE_2(SYMCLK32_LE_CNTL,

				SYMCLK32_LE0_SRC_SEL, phyd32clk,

				SYMCLK32_LE0_EN, 1);

		break;

	case 1:

		if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

			REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,

					SYMCLK32_LE1_GATE_DISABLE, 1,

					SYMCLK32_ROOT_LE1_GATE_DISABLE, 1);

		REG_UPDATE_2(SYMCLK32_LE_CNTL,

				SYMCLK32_LE1_SRC_SEL, phyd32clk,

				SYMCLK32_LE1_EN, 1);
@@ -319,19 +311,38 @@ void dccg31_disable_symclk32_le( 
		REG_UPDATE_2(SYMCLK32_LE_CNTL,

				SYMCLK32_LE0_SRC_SEL, 0,

				SYMCLK32_LE0_EN, 0);

		if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

			REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,

					SYMCLK32_LE0_GATE_DISABLE, 0,

					SYMCLK32_ROOT_LE0_GATE_DISABLE, 0);

		break;

	case 1:

		REG_UPDATE_2(SYMCLK32_LE_CNTL,

				SYMCLK32_LE1_SRC_SEL, 0,

				SYMCLK32_LE1_EN, 0);

		if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

		break;

	default:

		BREAK_TO_DEBUGGER();

		return;

	}

}



void dccg31_set_symclk32_le_root_clock_gating(

		struct dccg *dccg,

		int hpo_le_inst,

		bool enable)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);



	if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

		return;



	switch (hpo_le_inst) {

	case 0:

		REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,

					SYMCLK32_LE1_GATE_DISABLE, 0,

					SYMCLK32_ROOT_LE1_GATE_DISABLE, 0);

				SYMCLK32_LE0_GATE_DISABLE, enable ? 1 : 0,

				SYMCLK32_ROOT_LE0_GATE_DISABLE, enable ? 1 : 0);

		break;

	case 1:

		REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,

				SYMCLK32_LE1_GATE_DISABLE, enable ? 1 : 0,

				SYMCLK32_ROOT_LE1_GATE_DISABLE, enable ? 1 : 0);

		break;

	default:

		BREAK_TO_DEBUGGER();
@@ -660,10 +671,8 @@ void dccg31_init(struct dccg *dccg) 
	dccg31_disable_symclk32_se(dccg, 2);

	dccg31_disable_symclk32_se(dccg, 3);



	if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) {

		dccg31_disable_symclk32_le(dccg, 0);

		dccg31_disable_symclk32_le(dccg, 1);

	}

	dccg31_set_symclk32_le_root_clock_gating(dccg, 0, false);

	dccg31_set_symclk32_le_root_clock_gating(dccg, 1, false);



	if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

		dccg31_disable_dpstreamclk(dccg, 0);

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h

+5 −0
Original line number Diff line number Diff line
@@ -179,6 +179,11 @@ void dccg31_disable_symclk32_le( 
		struct dccg *dccg,

		int hpo_le_inst);



void dccg31_set_symclk32_le_root_clock_gating(

		struct dccg *dccg,

		int hpo_le_inst,

		bool enable);



void dccg31_set_physymclk(

		struct dccg *dccg,

		int phy_inst,

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c

+1 −0
Original line number Diff line number Diff line
@@ -362,6 +362,7 @@ static const struct dccg_funcs dccg314_funcs = { 
	.disable_symclk32_se = dccg31_disable_symclk32_se,

	.enable_symclk32_le = dccg31_enable_symclk32_le,

	.disable_symclk32_le = dccg31_disable_symclk32_le,

	.set_symclk32_le_root_clock_gating = dccg31_set_symclk32_le_root_clock_gating,

	.set_physymclk = dccg31_set_physymclk,

	.set_dtbclk_dto = dccg314_set_dtbclk_dto,

	.set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

+5 −0
Original line number Diff line number Diff line
@@ -123,6 +123,11 @@ struct dccg_funcs { 
			struct dccg *dccg,

			int hpo_le_inst);



	void (*set_symclk32_le_root_clock_gating)(

			struct dccg *dccg,

			int hpo_le_inst,

			bool enable);



	void (*set_physymclk)(

			struct dccg *dccg,

			int phy_inst,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

+10 −0
Original line number Diff line number Diff line
@@ -108,6 +108,11 @@ static void enable_hpo_dp_link_output(struct dc_link *link, 
		enum clock_source_id clock_source,

		const struct dc_link_settings *link_settings)

{

	if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating)

		link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating(

				link->dc->res_pool->dccg,

				link_res->hpo_dp_link_enc->inst,

				true);

	link_res->hpo_dp_link_enc->funcs->enable_link_phy(

			link_res->hpo_dp_link_enc,

			link_settings,
@@ -122,6 +127,11 @@ static void disable_hpo_dp_link_output(struct dc_link *link, 
		link_res->hpo_dp_link_enc->funcs->link_disable(link_res->hpo_dp_link_enc);

		link_res->hpo_dp_link_enc->funcs->disable_link_phy(

				link_res->hpo_dp_link_enc, signal);

		if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating)

			link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating(

					link->dc->res_pool->dccg,

					link_res->hpo_dp_link_enc->inst,

					false);

}



static void set_hpo_dp_link_test_pattern(struct dc_link *link,