Commit 43df4eb2 authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer
Browse files

MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDS 



SB1250 uart bug is related to PASS 2 workarounds. Use config
CONFIG_SB1_PASS_2_WORKAROUNDS directly and get rid of SIBYTE_1956_WAR.

Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent a7fbed98

arch/mips/include/asm/mach-cavium-octeon/war.h

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Original line number Diff line number Diff line
@@ -10,7 +10,6 @@ 
#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H



#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0



#define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR	\

	OCTEON_IS_MODEL(OCTEON_CN6XXX)

arch/mips/include/asm/mach-generic/war.h

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Original line number Diff line number Diff line
@@ -9,6 +9,5 @@ 
#define __ASM_MACH_GENERIC_WAR_H



#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0



#endif /* __ASM_MACH_GENERIC_WAR_H */

arch/mips/include/asm/mach-ip22/war.h

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Original line number Diff line number Diff line
@@ -9,6 +9,5 @@ 
#define __ASM_MIPS_MACH_IP22_WAR_H



#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0



#endif /* __ASM_MIPS_MACH_IP22_WAR_H */

arch/mips/include/asm/mach-ip27/war.h

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Original line number Diff line number Diff line
@@ -9,6 +9,5 @@ 
#define __ASM_MIPS_MACH_IP27_WAR_H



#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0



#endif /* __ASM_MIPS_MACH_IP27_WAR_H */

arch/mips/include/asm/mach-ip28/war.h

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Original line number Diff line number Diff line
@@ -9,6 +9,5 @@ 
#define __ASM_MIPS_MACH_IP28_WAR_H



#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0



#endif /* __ASM_MIPS_MACH_IP28_WAR_H */