Commit a7fbed98 authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer
Browse files

MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config option 



Use a new config option to enable MIPS 34K ITLB workaround and remove
define from different war.h files.

Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 256ec489

arch/mips/Kconfig

+4 −0
Original line number Diff line number Diff line
@@ -2683,6 +2683,10 @@ config WAR_ICACHE_REFILLS 
config WAR_R10000_LLSC

	bool



# 34K core erratum: "Problems Executing the TLBR Instruction"

config WAR_MIPS34K_MISSED_ITLB

	bool



#

# - Highmem only makes sense for the 32-bit kernel.

# - The current highmem code will only work properly on physically indexed

arch/mips/include/asm/mach-cavium-octeon/war.h

+0 −1
Original line number Diff line number Diff line
@@ -11,7 +11,6 @@ 


#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS34K_MISSED_ITLB_WAR		0



#define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR	\

	OCTEON_IS_MODEL(OCTEON_CN6XXX)

arch/mips/include/asm/mach-generic/war.h

+0 −1
Original line number Diff line number Diff line
@@ -10,6 +10,5 @@ 


#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS34K_MISSED_ITLB_WAR		0



#endif /* __ASM_MACH_GENERIC_WAR_H */

arch/mips/include/asm/mach-ip22/war.h

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Original line number Diff line number Diff line
@@ -10,6 +10,5 @@ 


#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS34K_MISSED_ITLB_WAR		0



#endif /* __ASM_MIPS_MACH_IP22_WAR_H */

arch/mips/include/asm/mach-ip27/war.h

+0 −1
Original line number Diff line number Diff line
@@ -10,6 +10,5 @@ 


#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS34K_MISSED_ITLB_WAR		0



#endif /* __ASM_MIPS_MACH_IP27_WAR_H */