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Commit 47ed4e1c authored by Ken Wang's avatar Ken Wang Committed by Alex Deucher
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drm/amdgpu: add workaround for S3 issues on some vega10 boards 



Certain MC registers need a delay after writing them to properly
update in the init sequence.

Signed-off-by: default avatarKen Wang <Ken.Wang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4426826c
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