Commit 4c3861f5 authored by Rodrigo Siqueira's avatar Rodrigo Siqueira Committed by Alex Deucher
Browse files

drm/amd/display: Create FPU files for DCN314 



DCN314 has multiple references to FPU operations inside the resource
files, and we need to move those codes to the DML folder. This commit
creates the dcn314_fpu files and moves the bounding box operation to
this file.

Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 89390c49

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c

+4 −231
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ 
#include "dce110/dce110_resource.h"

#include "dml/display_mode_vba.h"

#include "dml/dcn31/dcn31_fpu.h"

#include "dml/dcn314/dcn314_fpu.h"

#include "dcn314/dcn314_dccg.h"

#include "dcn10/dcn10_resource.h"

#include "dcn31/dcn31_panel_cntl.h"
@@ -132,155 +133,6 @@ static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C 


#define DC_LOGGER_INIT(logger)



#define DCN3_14_DEFAULT_DET_SIZE 384

#define DCN3_14_MAX_DET_SIZE 384

#define DCN3_14_MIN_COMPBUF_SIZE_KB 128

#define DCN3_14_CRB_SEGMENT_SIZE_KB 64

struct _vcs_dpi_ip_params_st dcn3_14_ip = {

	.VBlankNomDefaultUS = 668,

	.gpuvm_enable = 1,

	.gpuvm_max_page_table_levels = 1,

	.hostvm_enable = 1,

	.hostvm_max_page_table_levels = 2,

	.rob_buffer_size_kbytes = 64,

	.det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE,

	.config_return_buffer_size_in_kbytes = 1792,

	.compressed_buffer_segment_size_in_kbytes = 64,

	.meta_fifo_size_in_kentries = 32,

	.zero_size_buffer_entries = 512,

	.compbuf_reserved_space_64b = 256,

	.compbuf_reserved_space_zs = 64,

	.dpp_output_buffer_pixels = 2560,

	.opp_output_buffer_lines = 1,

	.pixel_chunk_size_kbytes = 8,

	.meta_chunk_size_kbytes = 2,

	.min_meta_chunk_size_bytes = 256,

	.writeback_chunk_size_kbytes = 8,

	.ptoi_supported = false,

	.num_dsc = 4,

	.maximum_dsc_bits_per_component = 10,

	.dsc422_native_support = false,

	.is_line_buffer_bpp_fixed = true,

	.line_buffer_fixed_bpp = 48,

	.line_buffer_size_bits = 789504,

	.max_line_buffer_lines = 12,

	.writeback_interface_buffer_size_kbytes = 90,

	.max_num_dpp = 4,

	.max_num_otg = 4,

	.max_num_hdmi_frl_outputs = 1,

	.max_num_wb = 1,

	.max_dchub_pscl_bw_pix_per_clk = 4,

	.max_pscl_lb_bw_pix_per_clk = 2,

	.max_lb_vscl_bw_pix_per_clk = 4,

	.max_vscl_hscl_bw_pix_per_clk = 4,

	.max_hscl_ratio = 6,

	.max_vscl_ratio = 6,

	.max_hscl_taps = 8,

	.max_vscl_taps = 8,

	.dpte_buffer_size_in_pte_reqs_luma = 64,

	.dpte_buffer_size_in_pte_reqs_chroma = 34,

	.dispclk_ramp_margin_percent = 1,

	.max_inter_dcn_tile_repeaters = 8,

	.cursor_buffer_size = 16,

	.cursor_chunk_size = 2,

	.writeback_line_buffer_buffer_size = 0,

	.writeback_min_hscl_ratio = 1,

	.writeback_min_vscl_ratio = 1,

	.writeback_max_hscl_ratio = 1,

	.writeback_max_vscl_ratio = 1,

	.writeback_max_hscl_taps = 1,

	.writeback_max_vscl_taps = 1,

	.dppclk_delay_subtotal = 46,

	.dppclk_delay_scl = 50,

	.dppclk_delay_scl_lb_only = 16,

	.dppclk_delay_cnvc_formatter = 27,

	.dppclk_delay_cnvc_cursor = 6,

	.dispclk_delay_subtotal = 119,

	.dynamic_metadata_vm_enabled = false,

	.odm_combine_4to1_supported = false,

	.dcc_supported = true,

};



struct _vcs_dpi_soc_bounding_box_st dcn3_14_soc = {

		/*TODO: correct dispclk/dppclk voltage level determination*/

	.clock_limits = {

		{

			.state = 0,

			.dispclk_mhz = 1200.0,

			.dppclk_mhz = 1200.0,

			.phyclk_mhz = 600.0,

			.phyclk_d18_mhz = 667.0,

			.dscclk_mhz = 186.0,

			.dtbclk_mhz = 625.0,

		},

		{

			.state = 1,

			.dispclk_mhz = 1200.0,

			.dppclk_mhz = 1200.0,

			.phyclk_mhz = 810.0,

			.phyclk_d18_mhz = 667.0,

			.dscclk_mhz = 209.0,

			.dtbclk_mhz = 625.0,

		},

		{

			.state = 2,

			.dispclk_mhz = 1200.0,

			.dppclk_mhz = 1200.0,

			.phyclk_mhz = 810.0,

			.phyclk_d18_mhz = 667.0,

			.dscclk_mhz = 209.0,

			.dtbclk_mhz = 625.0,

		},

		{

			.state = 3,

			.dispclk_mhz = 1200.0,

			.dppclk_mhz = 1200.0,

			.phyclk_mhz = 810.0,

			.phyclk_d18_mhz = 667.0,

			.dscclk_mhz = 371.0,

			.dtbclk_mhz = 625.0,

		},

		{

			.state = 4,

			.dispclk_mhz = 1200.0,

			.dppclk_mhz = 1200.0,

			.phyclk_mhz = 810.0,

			.phyclk_d18_mhz = 667.0,

			.dscclk_mhz = 417.0,

			.dtbclk_mhz = 625.0,

		},

	},

	.num_states = 5,

	.sr_exit_time_us = 9.0,

	.sr_enter_plus_exit_time_us = 11.0,

	.sr_exit_z8_time_us = 442.0,

	.sr_enter_plus_exit_z8_time_us = 560.0,

	.writeback_latency_us = 12.0,

	.dram_channel_width_bytes = 4,

	.round_trip_ping_latency_dcfclk_cycles = 106,

	.urgent_latency_pixel_data_only_us = 4.0,

	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,

	.urgent_latency_vm_data_only_us = 4.0,

	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,

	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,

	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,

	.pct_ideal_sdp_bw_after_urgent = 80.0,

	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,

	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,

	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,

	.max_avg_sdp_bw_use_normal_percent = 60.0,

	.max_avg_dram_bw_use_normal_percent = 60.0,

	.fabric_datapath_to_dcn_data_return_bytes = 32,

	.return_bus_width_bytes = 64,

	.downspread_percent = 0.38,

	.dcn_downspread_percent = 0.5,

	.gpuvm_min_page_size_bytes = 4096,

	.hostvm_min_page_size_bytes = 4096,

	.do_urgent_latency_adjustment = false,

	.urgent_latency_adjustment_fabric_clock_component_us = 0,

	.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,

};



enum dcn31_clk_src_array_id {

	DCN31_CLK_SRC_PLL0,

	DCN31_CLK_SRC_PLL1,
@@ -1906,88 +1758,9 @@ static struct dc_cap_funcs cap_funcs = { 


static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

{

	struct clk_limit_table *clk_table = &bw_params->clk_table;

	struct _vcs_dpi_voltage_scaling_st *clock_tmp = dcn3_14_soc._clock_tmp;

	unsigned int i, closest_clk_lvl;

	int max_dispclk_mhz = 0, max_dppclk_mhz = 0;

	int j;



	// Default clock levels are used for diags, which may lead to overclocking.

	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {



		dcn3_14_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;

		dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count;



		if (bw_params->num_channels > 0)

			dcn3_14_soc.num_chans = bw_params->num_channels;



		ASSERT(dcn3_14_soc.num_chans);

		ASSERT(clk_table->num_entries);



		/* Prepass to find max clocks independent of voltage level. */

		for (i = 0; i < clk_table->num_entries; ++i) {

			if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)

				max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;

			if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)

				max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;

		}



		for (i = 0; i < clk_table->num_entries; i++) {

			/* loop backwards*/

			for (closest_clk_lvl = 0, j = dcn3_14_soc.num_states - 1; j >= 0; j--) {

				if ((unsigned int) dcn3_14_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {

					closest_clk_lvl = j;

					break;

				}

			}

			if (clk_table->num_entries == 1) {

				/*smu gives one DPM level, let's take the highest one*/

				closest_clk_lvl = dcn3_14_soc.num_states - 1;

			}



			clock_tmp[i].state = i;



			/* Clocks dependent on voltage level. */

			clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;

			if (clk_table->num_entries == 1 &&

				clock_tmp[i].dcfclk_mhz < dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {

				/*SMU fix not released yet*/

				clock_tmp[i].dcfclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;

			}

			clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;

			clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz;



			if (clk_table->entries[i].memclk_mhz && clk_table->entries[i].wck_ratio)

				clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;



			/* Clocks independent of voltage level. */

			clock_tmp[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :

				dcn3_14_soc.clock_limits[closest_clk_lvl].dispclk_mhz;



			clock_tmp[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :

				dcn3_14_soc.clock_limits[closest_clk_lvl].dppclk_mhz;



			clock_tmp[i].dram_bw_per_chan_gbps = dcn3_14_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;

			clock_tmp[i].dscclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dscclk_mhz;

			clock_tmp[i].dtbclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;

			clock_tmp[i].phyclk_d18_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;

			clock_tmp[i].phyclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].phyclk_mhz;

		}

		for (i = 0; i < clk_table->num_entries; i++)

			dcn3_14_soc.clock_limits[i] = clock_tmp[i];

		if (clk_table->num_entries)

			dcn3_14_soc.num_states = clk_table->num_entries;

	}



	if (max_dispclk_mhz) {

		dcn3_14_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;

		dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;

	}



	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))

		dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN31);

	else

		dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN31_FPGA);

	DC_FP_START();

	dcn314_update_bw_bounding_box_fpu(dc, bw_params);

	DC_FP_END();

}



static struct resource_funcs dcn314_res_pool_funcs = {

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.h

+3 −0
Original line number Diff line number Diff line
@@ -29,6 +29,9 @@ 


#include "core_types.h"



extern struct _vcs_dpi_ip_params_st dcn3_14_ip;

extern struct _vcs_dpi_soc_bounding_box_st dcn3_14_soc;



#define TO_DCN314_RES_POOL(pool)\

	container_of(pool, struct dcn314_resource_pool, base)

drivers/gpu/drm/amd/display/dc/dml/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_ccflags) $(fram 
CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_ccflags) $(frame_warn_flag)

CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml/dcn314/dcn314_fpu.o := $(dml_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/dcn30_fpu.o := $(dml_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/dcn32_fpu.o := $(dml_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_32.o := $(dml_ccflags) $(frame_warn_flag)
@@ -129,6 +130,7 @@ DML += dcn321/dcn321_fpu.o 
DML += dcn301/dcn301_fpu.o

DML += dcn302/dcn302_fpu.o

DML += dcn303/dcn303_fpu.o

DML += dcn314/dcn314_fpu.o

DML += dsc/rc_calc_fpu.o

DML += calcs/dcn_calcs.o calcs/dcn_calc_math.o calcs/dcn_calc_auto.o

endif

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

0 → 100644
+266 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: MIT

/*

 * Copyright 2022 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */



#include "clk_mgr.h"

#include "resource.h"

#include "dcn314_fpu.h"

#include "dml/display_mode_vba.h"



struct _vcs_dpi_ip_params_st dcn3_14_ip = {

	.VBlankNomDefaultUS = 668,

	.gpuvm_enable = 1,

	.gpuvm_max_page_table_levels = 1,

	.hostvm_enable = 1,

	.hostvm_max_page_table_levels = 2,

	.rob_buffer_size_kbytes = 64,

	.det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE,

	.config_return_buffer_size_in_kbytes = 1792,

	.compressed_buffer_segment_size_in_kbytes = 64,

	.meta_fifo_size_in_kentries = 32,

	.zero_size_buffer_entries = 512,

	.compbuf_reserved_space_64b = 256,

	.compbuf_reserved_space_zs = 64,

	.dpp_output_buffer_pixels = 2560,

	.opp_output_buffer_lines = 1,

	.pixel_chunk_size_kbytes = 8,

	.meta_chunk_size_kbytes = 2,

	.min_meta_chunk_size_bytes = 256,

	.writeback_chunk_size_kbytes = 8,

	.ptoi_supported = false,

	.num_dsc = 4,

	.maximum_dsc_bits_per_component = 10,

	.dsc422_native_support = false,

	.is_line_buffer_bpp_fixed = true,

	.line_buffer_fixed_bpp = 48,

	.line_buffer_size_bits = 789504,

	.max_line_buffer_lines = 12,

	.writeback_interface_buffer_size_kbytes = 90,

	.max_num_dpp = 4,

	.max_num_otg = 4,

	.max_num_hdmi_frl_outputs = 1,

	.max_num_wb = 1,

	.max_dchub_pscl_bw_pix_per_clk = 4,

	.max_pscl_lb_bw_pix_per_clk = 2,

	.max_lb_vscl_bw_pix_per_clk = 4,

	.max_vscl_hscl_bw_pix_per_clk = 4,

	.max_hscl_ratio = 6,

	.max_vscl_ratio = 6,

	.max_hscl_taps = 8,

	.max_vscl_taps = 8,

	.dpte_buffer_size_in_pte_reqs_luma = 64,

	.dpte_buffer_size_in_pte_reqs_chroma = 34,

	.dispclk_ramp_margin_percent = 1,

	.max_inter_dcn_tile_repeaters = 8,

	.cursor_buffer_size = 16,

	.cursor_chunk_size = 2,

	.writeback_line_buffer_buffer_size = 0,

	.writeback_min_hscl_ratio = 1,

	.writeback_min_vscl_ratio = 1,

	.writeback_max_hscl_ratio = 1,

	.writeback_max_vscl_ratio = 1,

	.writeback_max_hscl_taps = 1,

	.writeback_max_vscl_taps = 1,

	.dppclk_delay_subtotal = 46,

	.dppclk_delay_scl = 50,

	.dppclk_delay_scl_lb_only = 16,

	.dppclk_delay_cnvc_formatter = 27,

	.dppclk_delay_cnvc_cursor = 6,

	.dispclk_delay_subtotal = 119,

	.dynamic_metadata_vm_enabled = false,

	.odm_combine_4to1_supported = false,

	.dcc_supported = true,

};



struct _vcs_dpi_soc_bounding_box_st dcn3_14_soc = {

		/*TODO: correct dispclk/dppclk voltage level determination*/

	.clock_limits = {

		{

			.state = 0,

			.dispclk_mhz = 1200.0,

			.dppclk_mhz = 1200.0,

			.phyclk_mhz = 600.0,

			.phyclk_d18_mhz = 667.0,

			.dscclk_mhz = 186.0,

			.dtbclk_mhz = 625.0,

		},

		{

			.state = 1,

			.dispclk_mhz = 1200.0,

			.dppclk_mhz = 1200.0,

			.phyclk_mhz = 810.0,

			.phyclk_d18_mhz = 667.0,

			.dscclk_mhz = 209.0,

			.dtbclk_mhz = 625.0,

		},

		{

			.state = 2,

			.dispclk_mhz = 1200.0,

			.dppclk_mhz = 1200.0,

			.phyclk_mhz = 810.0,

			.phyclk_d18_mhz = 667.0,

			.dscclk_mhz = 209.0,

			.dtbclk_mhz = 625.0,

		},

		{

			.state = 3,

			.dispclk_mhz = 1200.0,

			.dppclk_mhz = 1200.0,

			.phyclk_mhz = 810.0,

			.phyclk_d18_mhz = 667.0,

			.dscclk_mhz = 371.0,

			.dtbclk_mhz = 625.0,

		},

		{

			.state = 4,

			.dispclk_mhz = 1200.0,

			.dppclk_mhz = 1200.0,

			.phyclk_mhz = 810.0,

			.phyclk_d18_mhz = 667.0,

			.dscclk_mhz = 417.0,

			.dtbclk_mhz = 625.0,

		},

	},

	.num_states = 5,

	.sr_exit_time_us = 9.0,

	.sr_enter_plus_exit_time_us = 11.0,

	.sr_exit_z8_time_us = 442.0,

	.sr_enter_plus_exit_z8_time_us = 560.0,

	.writeback_latency_us = 12.0,

	.dram_channel_width_bytes = 4,

	.round_trip_ping_latency_dcfclk_cycles = 106,

	.urgent_latency_pixel_data_only_us = 4.0,

	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,

	.urgent_latency_vm_data_only_us = 4.0,

	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,

	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,

	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,

	.pct_ideal_sdp_bw_after_urgent = 80.0,

	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,

	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,

	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,

	.max_avg_sdp_bw_use_normal_percent = 60.0,

	.max_avg_dram_bw_use_normal_percent = 60.0,

	.fabric_datapath_to_dcn_data_return_bytes = 32,

	.return_bus_width_bytes = 64,

	.downspread_percent = 0.38,

	.dcn_downspread_percent = 0.5,

	.gpuvm_min_page_size_bytes = 4096,

	.hostvm_min_page_size_bytes = 4096,

	.do_urgent_latency_adjustment = false,

	.urgent_latency_adjustment_fabric_clock_component_us = 0,

	.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,

};





void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)

{

	struct clk_limit_table *clk_table = &bw_params->clk_table;

	struct _vcs_dpi_voltage_scaling_st *clock_limits =

		dcn3_14_soc.clock_limits;

	unsigned int i, closest_clk_lvl;

	int max_dispclk_mhz = 0, max_dppclk_mhz = 0;

	int j;



	dc_assert_fp_enabled();



	// Default clock levels are used for diags, which may lead to overclocking.

	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {



		dcn3_14_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;

		dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count;



		if (bw_params->num_channels > 0)

			dcn3_14_soc.num_chans = bw_params->num_channels;



		ASSERT(dcn3_14_soc.num_chans);

		ASSERT(clk_table->num_entries);



		/* Prepass to find max clocks independent of voltage level. */

		for (i = 0; i < clk_table->num_entries; ++i) {

			if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)

				max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;

			if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)

				max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;

		}



		for (i = 0; i < clk_table->num_entries; i++) {

			/* loop backwards*/

			for (closest_clk_lvl = 0, j = dcn3_14_soc.num_states - 1; j >= 0; j--) {

				if ((unsigned int) dcn3_14_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {

					closest_clk_lvl = j;

					break;

				}

			}

			if (clk_table->num_entries == 1) {

				/*smu gives one DPM level, let's take the highest one*/

				closest_clk_lvl = dcn3_14_soc.num_states - 1;

			}



			clock_limits[i].state = i;



			/* Clocks dependent on voltage level. */

			clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;

			if (clk_table->num_entries == 1 &&

				clock_limits[i].dcfclk_mhz < dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {

				/*SMU fix not released yet*/

				clock_limits[i].dcfclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;

			}

			clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;

			clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;



			if (clk_table->entries[i].memclk_mhz && clk_table->entries[i].wck_ratio)

				clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;



			/* Clocks independent of voltage level. */

			clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :

				dcn3_14_soc.clock_limits[closest_clk_lvl].dispclk_mhz;



			clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :

				dcn3_14_soc.clock_limits[closest_clk_lvl].dppclk_mhz;



			clock_limits[i].dram_bw_per_chan_gbps = dcn3_14_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;

			clock_limits[i].dscclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dscclk_mhz;

			clock_limits[i].dtbclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;

			clock_limits[i].phyclk_d18_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;

			clock_limits[i].phyclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].phyclk_mhz;

		}

		for (i = 0; i < clk_table->num_entries; i++)

			dcn3_14_soc.clock_limits[i] = clock_limits[i];

		if (clk_table->num_entries) {

			dcn3_14_soc.num_states = clk_table->num_entries;

		}

	}



	if (max_dispclk_mhz) {

		dcn3_14_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;

		dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;

	}



	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))

		dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN31);

	else

		dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN31_FPGA);

}

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.h

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Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT */

/*

 * Copyright 2022 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */



#ifndef __DCN314_FPU_H__

#define __DCN314_FPU_H__



#define DCN3_14_DEFAULT_DET_SIZE 384

#define DCN3_14_MAX_DET_SIZE 384

#define DCN3_14_MIN_COMPBUF_SIZE_KB 128

#define DCN3_14_CRB_SEGMENT_SIZE_KB 64



void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);



#endif