Commit 4e218727 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Greg Kroah-Hartman
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coresight: etm4x: Update TRCIDR3.NUMPROCS handling to match v4.2 



Since ETMv4.2, TRCIDR3.NUMPROCS has been extended to a 5bit field
by encoding the top 2 bits[4:3] in TRCIDR3.[13:12], which were RES0.
Fix the driver to compute the field correctly for ETMv4.2+

Cc: Mike Leach <mike.leach@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20201127175256.1092685-6-mathieu.poirier@linaro.org


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent f2603b22

drivers/hwtracing/coresight/coresight-etm4x-core.c

+7 −2
Original line number Diff line number Diff line
@@ -724,8 +724,13 @@ static void etm4_init_arch_data(void *info) 
	else

		drvdata->sysstall = false;



	/* NUMPROC, bits[30:28] the number of PEs available for tracing */

	drvdata->nr_pe = BMVAL(etmidr3, 28, 30);

	/*

	 * NUMPROC - the number of PEs available for tracing, 5bits

	 *         = TRCIDR3.bits[13:12]bits[30:28]

	 *  bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0)

	 *  bits[3:0] = TRCIDR3.bits[30:28]

	 */

	drvdata->nr_pe = (BMVAL(etmidr3, 12, 13) << 3) | BMVAL(etmidr3, 28, 30);



	/* NOOVERFLOW, bit[31] is trace overflow prevention supported */

	if (BMVAL(etmidr3, 31, 31))