Commit 4fa1edc8 authored Mar 03, 2022 by Biju Das Committed by Geert Uytterhoeven Apr 04, 2022

arm64: dts: renesas: rzg2lc-smarc: Enable i2c{0,1,2}

Enable i2c{0,1} on RZ/G2LC SMARC EVK by deleting respective
entries from board dts and adding pincontrol entries to the
soc-pinctrl dtsi. Also enable i2c2 by adding to soc dtsi.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220303164155.7706-4-biju.das.jz@bp.renesas.com

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

parent 0a7c1c88

arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts

+0 −12

Original line number	Diff line number	Diff line
		@@ -14,18 +14,6 @@ / {
		compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
		};

		&i2c0 {
		/delete-property/ pinctrl-0;
		/delete-property/ pinctrl-names;
		status = "disabled";
		};

		&i2c1 {
		/delete-property/ pinctrl-0;
		/delete-property/ pinctrl-names;
		status = "disabled";
		};

		&spi1 {
		/delete-property/ pinctrl-0;
		/delete-property/ pinctrl-names;

arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi

+15 −0

Original line number	Diff line number	Diff line
		@@ -35,6 +35,21 @@ can1_pins: can1 {
		};
		#endif

		i2c0_pins: i2c0 {
		pins = "RIIC0_SDA", "RIIC0_SCL";
		input-enable;
		};

		i2c1_pins: i2c1 {
		pins = "RIIC1_SDA", "RIIC1_SCL";
		input-enable;
		};

		i2c2_pins: i2c2 {
		pinmux = <RZG2L_PORT_PINMUX(42, 3, 1)>, /* SDA */
		<RZG2L_PORT_PINMUX(42, 4, 1)>; /* SCL */
		};

		scif0_pins: scif0 {
		pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
		<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */

arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi

+5 −1

Original line number	Diff line number	Diff line
		@@ -61,7 +61,11 @@ &canfd {
		#endif

		&i2c2 {
		status = "disabled";
		pinctrl-0 = <&i2c2_pins>;
		pinctrl-names = "default";
		clock-frequency = <400000>;

		status = "okay";

		wm8978: codec@1a {
		compatible = "wlf,wm8978";