Commit 576418e3 authored by Biju Das's avatar Biju Das Committed by Stephen Boyd
Browse files

clk: vc3: Fix 64 by 64 division 



Fix the below cocci warnings by replacing do_div()->div64_ul() and
bound the result with a max value of U16_MAX.

cocci warnings:
	drivers/clk/clk-versaclock3.c:404:2-8: WARNING: do_div() does a
	64-by-32 division, please consider using div64_ul instead.

Reported-by: default avatarJulia Lawall <julia.lawall@inria.fr>
Closes: https://lore.kernel.org/r/202307270841.yr5HxYIl-lkp@intel.com/


Fixes: 6e9aff55 ("clk: Add support for versa3 clock driver")
Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20230824104812.147775-3-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 1aa2a9f2

drivers/clk/clk-versaclock3.c

+2 −3
Original line number Diff line number Diff line
@@ -401,11 +401,10 @@ static long vc3_pll_round_rate(struct clk_hw *hw, unsigned long rate, 
		/* Determine best fractional part, which is 16 bit wide */

		div_frc = rate % *parent_rate;

		div_frc *= BIT(16) - 1;

		do_div(div_frc, *parent_rate);



		vc3->div_frc = (u32)div_frc;

		vc3->div_frc = min_t(u64, div64_ul(div_frc, *parent_rate), U16_MAX);

		rate = (*parent_rate *

			(vc3->div_int * VC3_2_POW_16 + div_frc) / VC3_2_POW_16);

			(vc3->div_int * VC3_2_POW_16 + vc3->div_frc) / VC3_2_POW_16);

	} else {

		rate = *parent_rate * vc3->div_int;

	}