Commit 5cc4e71f authored by Antonio Borneo's avatar Antonio Borneo Committed by Philippe Cornu
Browse files

drm/stm: dsi: compute the transition time from LP to HS and back 



The driver uses a conservative set of hardcoded values for the
maximum time delay of the transitions between LP and HS, either
for data and clock lanes.

By using the info in STM32MP157 datasheet, valid also for other ST
devices, compute the actual delay from the lane's bps.

Signed-off-by: default avatarAntonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: default avatarPhilippe Cornu <philippe.cornu@foss.st.com>
Acked-by: default avatarPhilippe Cornu <philippe.cornu@foss.st.com>
Signed-off-by: default avatarPhilippe Cornu <philippe.cornu@foss.st.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210713144941.3599-1-antonio.borneo@foss.st.com
parent 648ce7fd

drivers/gpu/drm/stm/dw_mipi_dsi-stm.c

+13 −4
Original line number Diff line number Diff line
@@ -309,14 +309,23 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, 
	return 0;

}



#define DSI_PHY_DELAY(fp, vp, mbps) DIV_ROUND_UP((fp) * (mbps) + 1000 * (vp), 8000)



static int

dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,

			   struct dw_mipi_dsi_dphy_timing *timing)

{

	timing->clk_hs2lp = 0x40;

	timing->clk_lp2hs = 0x40;

	timing->data_hs2lp = 0x40;

	timing->data_lp2hs = 0x40;

	/*

	 * From STM32MP157 datasheet, valid for STM32F469, STM32F7x9, STM32H747

	 * phy_clkhs2lp_time = (272+136*UI)/(8*UI)

	 * phy_clklp2hs_time = (512+40*UI)/(8*UI)

	 * phy_hs2lp_time = (192+64*UI)/(8*UI)

	 * phy_lp2hs_time = (256+32*UI)/(8*UI)

	 */

	timing->clk_hs2lp = DSI_PHY_DELAY(272, 136, lane_mbps);

	timing->clk_lp2hs = DSI_PHY_DELAY(512, 40, lane_mbps);

	timing->data_hs2lp = DSI_PHY_DELAY(192, 64, lane_mbps);

	timing->data_lp2hs = DSI_PHY_DELAY(256, 32, lane_mbps);



	return 0;

}