drm/i915: Add chv cmnlane power wells

CHV has two display PHYs so there are also two cmnlane power wells. Add
the approriate code to power the wells up/down.

Like on VLV we do the cmnreset assert/deassert and the DPLL refclock
enabling at approriate times.

This code actually works on my bsw.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>