Commit 5ea1534e authored by James Morse's avatar James Morse Committed by Will Deacon
Browse files

arm64/sysreg: Standardise naming for ID_MMFR4_EL1 



To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.

Ensure symbols for the ID_MMFR4_EL1 register have an _EL1 suffix,
and use lower case in feature names where the arm-arm does the same.

No functional change.

Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-3-james.morse@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 37622bae

arch/arm64/include/asm/sysreg.h

+8 −8
Original line number Diff line number Diff line
@@ -742,14 +742,14 @@ 
#define ID_MMFR0_EL1_PMSA_SHIFT		4

#define ID_MMFR0_EL1_VMSA_SHIFT		0



#define ID_MMFR4_EVT_SHIFT		28

#define ID_MMFR4_CCIDX_SHIFT		24

#define ID_MMFR4_LSM_SHIFT		20

#define ID_MMFR4_HPDS_SHIFT		16

#define ID_MMFR4_CNP_SHIFT		12

#define ID_MMFR4_XNX_SHIFT		8

#define ID_MMFR4_AC2_SHIFT		4

#define ID_MMFR4_SPECSEI_SHIFT		0

#define ID_MMFR4_EL1_EVT_SHIFT		28

#define ID_MMFR4_EL1_CCIDX_SHIFT	24

#define ID_MMFR4_EL1_LSM_SHIFT		20

#define ID_MMFR4_EL1_HPDS_SHIFT		16

#define ID_MMFR4_EL1_CnP_SHIFT		12

#define ID_MMFR4_EL1_XNX_SHIFT		8

#define ID_MMFR4_EL1_AC2_SHIFT		4

#define ID_MMFR4_EL1_SpecSEI_SHIFT	0



#define ID_MMFR5_ETS_SHIFT		0

arch/arm64/kernel/cpufeature.c

+8 −8
Original line number Diff line number Diff line
@@ -491,13 +491,13 @@ static const struct arm64_ftr_bits ftr_id_isar5[] = { 
};



static const struct arm64_ftr_bits ftr_id_mmfr4[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0),



	/*

	 * SpecSEI = 1 indicates that the PE might generate an SError on an
@@ -505,7 +505,7 @@ static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 
	 * SError might be generated than it will not be. Hence it has been

	 * classified as FTR_HIGHER_SAFE.

	 */

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0),

	ARM64_FTR_END,

};