Commit 60f23414 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Vinod Koul
Browse files

phy: qcom-qmp: use QPHY_V4_PCS for ipq6018/ipq8074 PCIe gen3 



PCS_COM_* symbols duplicate the QPHY_V4_PCS_*. PCS_PCIE_* symbols
duplicate the QPHY_V4_PCS_PCIE_*. Use generic register names for the
IPQ6018 and IPQ8074 tables and drop the custom PCS_COM_*/PCS_PCIE*
names.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-8-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 6cad2983

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

+40 −40
Original line number Diff line number Diff line
@@ -354,25 +354,25 @@ static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { 
};



static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {

	QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),

	QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),

	QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),

	QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),

	QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),

	QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),

	QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),

};



static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = {

	QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),

	QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),

	QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),

	QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),

	QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),

	QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),

	QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),

	QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),

	QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),

};



static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
@@ -554,30 +554,30 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { 
};



static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = {

	QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL2, 0x83),

	QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_L, 0x9),

	QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_H_TOL, 0x42),

	QMP_PHY_INIT_CFG(PCS_COM_FLL_MAN_CODE, 0x40),

	QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),

	QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0),

	QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1),

	QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x0),

	QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),

	QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),

	QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),

	QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),

	QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),

	QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG2, 0xb),

	QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),

	QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),

	QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),

	QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),

	QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6),

	QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),

	QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),

	QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),

	QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),

	QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),

	QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),

};



static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {

drivers/phy/qualcomm/phy-qcom-qmp.h

+1 −34
Original line number Diff line number Diff line
@@ -64,40 +64,6 @@ 
#define QSERDES_PLL_SVS_MODE_CLK_SEL			0x194

#define QSERDES_PLL_CORECLK_DIV_MODE1			0x1b4



/* QMP V2 PHY for PCIE gen3 ports - PCS registers */



#define PCS_COM_FLL_CNTRL1				0x098

#define PCS_COM_FLL_CNTRL2				0x09c

#define PCS_COM_FLL_CNT_VAL_L				0x0a0

#define PCS_COM_FLL_CNT_VAL_H_TOL			0x0a4

#define PCS_COM_FLL_MAN_CODE				0x0a8

#define PCS_COM_REFGEN_REQ_CONFIG1			0x0dc

#define PCS_COM_G12S1_TXDEEMPH_M3P5DB			0x16c

#define PCS_COM_RX_SIGDET_LVL				0x188

#define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L		0x1a4

#define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H		0x1a8

#define PCS_COM_RX_DCC_CAL_CONFIG			0x1d8

#define PCS_COM_EQ_CONFIG5				0x1ec



/* QMP V2 PHY for PCIE gen3 ports - PCS Misc registers */



#define PCS_PCIE_POWER_STATE_CONFIG2			0x00c

#define PCS_PCIE_POWER_STATE_CONFIG4			0x014

#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE			0x01c

#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L		0x040

#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H		0x044

#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L		0x048

#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H		0x04c

#define PCS_PCIE_OSC_DTCT_CONFIG2			0x05c

#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2			0x078

#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4			0x080

#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5			0x084

#define PCS_PCIE_OSC_DTCT_ACTIONS			0x090

#define PCS_PCIE_EQ_CONFIG1				0x0a0

#define PCS_PCIE_EQ_CONFIG2				0x0a4

#define PCS_PCIE_PRESET_P10_PRE				0x0bc

#define PCS_PCIE_PRESET_P10_POST			0x0e0



/* Only for QMP V2 PHY - QSERDES COM registers */

#define QSERDES_COM_BG_TIMER				0x00c

#define QSERDES_COM_SSC_EN_CENTER			0x010
@@ -1014,6 +980,7 @@ 
#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L	0x48

#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1		0x50

#define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS		0x90

#define QPHY_V4_PCS_PCIE_EQ_CONFIG1			0xa0

#define QPHY_V4_PCS_PCIE_EQ_CONFIG2			0xa4

#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE		0xb4

#define QPHY_V4_PCS_PCIE_PRESET_P10_PRE			0xbc