Commit 630ea310 authored by Martin Blumenstingl's avatar Martin Blumenstingl Committed by Kevin Hilman
Browse files

ARM: dts: meson: provide the XTAL clock using a fixed-clock 



The clock controller driver has provided the XTAL clock so far. This
does not match how the hardware actually works because the XTAL clock is
an actual crystal which is mounted on the PCB.

Add the "xtal" clock to meson.dtsi and replace all references to the
clock controller's CLKID_XTAL with the new xtal clock node.

Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
parent 9cf79568

arch/arm/boot/dts/meson.dtsi

+7 −0
Original line number Diff line number Diff line
@@ -282,4 +282,11 @@ efuse: nvmem@0 { 
			};

		};

	};



	xtal: xtal-clk {

		compatible = "fixed-clock";

		clock-frequency = <24000000>;

		clock-output-names = "xtal";

		#clock-cells = <0>;

	};

}; /* end of / */

arch/arm/boot/dts/meson6.dtsi

+0 −7
Original line number Diff line number Diff line
@@ -36,13 +36,6 @@ apb2: bus@d0000000 { 
		ranges = <0x0 0xd0000000 0x40000>;

	};



	xtal: xtal-clk {

		compatible = "fixed-clock";

		clock-frequency = <24000000>;

		clock-output-names = "xtal";

		#clock-cells = <0>;

	};



	clk81: clk@0 {

		#clock-cells = <0>;

		compatible = "fixed-clock";

arch/arm/boot/dts/meson8.dtsi

+8 −7
Original line number Diff line number Diff line
@@ -455,6 +455,8 @@ &gpio_intc { 
&hhi {

	clkc: clock-controller {

		compatible = "amlogic,meson8-clkc";

		clocks = <&xtal>;

		clock-names = "xtal";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};
@@ -529,8 +531,7 @@ &rtc { 


&saradc {

	compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";

	clocks = <&clkc CLKID_XTAL>,

		<&clkc CLKID_SAR_ADC>;

	clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;

	clock-names = "clkin", "core";

	amlogic,hhi-sysctrl = <&hhi>;

	nvmem-cells = <&temperature_calib>;
@@ -548,31 +549,31 @@ &spifc { 
};



&timer_abcde {

	clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;

	clocks = <&xtal>, <&clkc CLKID_CLK81>;

	clock-names = "xtal", "pclk";

};



&uart_AO {

	compatible = "amlogic,meson8-uart", "amlogic,meson-uart";

	clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;

	clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>;

	clock-names = "baud", "xtal", "pclk";

};



&uart_A {

	compatible = "amlogic,meson8-uart", "amlogic,meson-uart";

	clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;

	clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>;

	clock-names = "baud", "xtal", "pclk";

};



&uart_B {

	compatible = "amlogic,meson8-uart", "amlogic,meson-uart";

	clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;

	clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>;

	clock-names = "baud", "xtal", "pclk";

};



&uart_C {

	compatible = "amlogic,meson8-uart", "amlogic,meson-uart";

	clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;

	clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>;

	clock-names = "baud", "xtal", "pclk";

};

arch/arm/boot/dts/meson8b-ec100.dts

+1 −1
Original line number Diff line number Diff line
@@ -377,7 +377,7 @@ &pwm_cd { 
	status = "okay";

	pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;

	pinctrl-names = "default";

	clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>;

	clocks = <&xtal>, <&xtal>;

	clock-names = "clkin0", "clkin1";

};

arch/arm/boot/dts/meson8b-mxq.dts

+1 −1
Original line number Diff line number Diff line
@@ -165,7 +165,7 @@ &pwm_cd { 
	status = "okay";

	pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;

	pinctrl-names = "default";

	clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>;

	clocks = <&xtal>, <&xtal>;

	clock-names = "clkin0", "clkin1";

};