ARM: dts: exynos: Reduce assigned-clocks entries for SPI0 on Artik5 board

Commit 2024b130 ("ARM: dts: exynos: Add Ethernet to Artik 5 board")
added ethernet chip on SPI0 bus and the whole bunch of assigned clock
entries to ensure proper clock rates and topology. Limit the assigned
clock parents only to the direct clocks of the SPI0 device and assume
that MPLL clock is already properly configured.

The applied clock topology was incorrect as some clocks between were
missing, what resulted in the following warning:

clk: failed to reparent div_mpll_pre to mout_mpll: -22

Fixes: 2024b130 ("ARM: dts: exynos: Add Ethernet to Artik 5 board")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/20201202122029.22198-1-m.szyprowski@samsung.com


Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>