Commit 7adf8410 authored by Haibo Chen's avatar Haibo Chen Committed by Shawn Guo
Browse files

arm64: dts: imx8ulp-evk: add 100MHz/200MHz pinctrl setting for eMMC 



Add 100MHz and 200MHz pinctrl setting for eMMC, and enable 8 bit bus mode
to config the eMMC work at HS400ES mode.

Also update to use Standard Drive Strength for USDHC pad to get a better
signal quality per Hardware team suggests.

Reviewed-by: default avatarSherry Sun <sherry.sun@nxp.com>
Signed-off-by: default avatarHaibo Chen <haibo.chen@nxp.com>
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 3d256330

arch/arm64/boot/dts/freescale/imx8ulp-evk.dts

+14 −12
Original line number Diff line number Diff line
@@ -119,9 +119,11 @@ &lpuart5 { 
};



&usdhc0 {

	pinctrl-names = "default", "sleep";

	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";

	pinctrl-0 = <&pinctrl_usdhc0>;

	pinctrl-1 = <&pinctrl_usdhc0>;

	pinctrl-2 = <&pinctrl_usdhc0>;

	pinctrl-3 = <&pinctrl_usdhc0>;

	non-removable;

	bus-width = <8>;

	status = "okay";
@@ -200,17 +202,17 @@ MX8ULP_PAD_PTF15__LPUART5_RX 0x3 


	pinctrl_usdhc0: usdhc0grp {

		fsl,pins = <

			MX8ULP_PAD_PTD1__SDHC0_CMD	0x43

			MX8ULP_PAD_PTD2__SDHC0_CLK	0x10042

			MX8ULP_PAD_PTD10__SDHC0_D0	0x43

			MX8ULP_PAD_PTD9__SDHC0_D1	0x43

			MX8ULP_PAD_PTD8__SDHC0_D2	0x43

			MX8ULP_PAD_PTD7__SDHC0_D3	0x43

			MX8ULP_PAD_PTD6__SDHC0_D4	0x43

			MX8ULP_PAD_PTD5__SDHC0_D5	0x43

			MX8ULP_PAD_PTD4__SDHC0_D6	0x43

			MX8ULP_PAD_PTD3__SDHC0_D7	0x43

			MX8ULP_PAD_PTD11__SDHC0_DQS	0x10042

			MX8ULP_PAD_PTD1__SDHC0_CMD	0x3

			MX8ULP_PAD_PTD2__SDHC0_CLK	0x10002

			MX8ULP_PAD_PTD10__SDHC0_D0	0x3

			MX8ULP_PAD_PTD9__SDHC0_D1	0x3

			MX8ULP_PAD_PTD8__SDHC0_D2	0x3

			MX8ULP_PAD_PTD7__SDHC0_D3	0x3

			MX8ULP_PAD_PTD6__SDHC0_D4	0x3

			MX8ULP_PAD_PTD5__SDHC0_D5	0x3

			MX8ULP_PAD_PTD4__SDHC0_D6	0x3

			MX8ULP_PAD_PTD3__SDHC0_D7	0x3

			MX8ULP_PAD_PTD11__SDHC0_DQS	0x10002

		>;

	};

};