MIPS: JZ4780: CI20: DTS: add SPI controller config

1. Add nodes for the two SPI controllers found in MIPS Creator CI20.
2. Reparent SPI clock source to effectively use MPLL and set its clock
   rate to 54MHz.

NOTE: To use the SPI controllers, `pinctrl-0` property must be set in
order to configure the used pins. As SPI functionality is multiplexed on
multiple pin groups, this choice is left to the user.

An example configuration:
```
 &spi0 {
         pinctrl-0 = <&pins_spi0>;
 }

 pins_spi0: spi0 {
         function = "ssi0";
         groups = "ssi0-dt-e", "ssi0-dr-e", "ssi0-clk-e",
                  "ssi0-ce0-e", "ssi0-ce1-e";
         bias-disable;
 };
```
Consult the CI20 pinout description for more details.

Signed-off-by: Artur Rojek <contact@artur-rojek.eu>
Link: https://lore.kernel.org/r/20210830230139.21476-4-contact@artur-rojek.eu


Signed-off-by: Mark Brown <broonie@kernel.org>