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Commit 8758109d authored by Apurva Nandan's avatar Apurva Nandan Committed by Vignesh Raghavendra
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arm64: dts: ti: k3-j784s4-mcu-wakeup: Add FSS OSPI0 and FSS OSPI1



TI K3 J784S4 has the Cadence OSPI controllers OSPI0 and OSPI1 on FSS
bus for interfacing with OSPI flashes. Add the nodes to allow using
SPI flashes.

Signed-off-by: default avatarApurva Nandan <a-nandan@ti.com>
Link: https://lore.kernel.org/r/20230504080305.38986-2-a-nandan@ti.com


Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
parent 2dc39c56
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