Commit 91dd3114 authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'intel-pinctrl-v6.2-1' of... 

Merge tag 'intel-pinctrl-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel

intel-pinctrl for v6.2-1

* Add Intel Moorefield pin control driver
* Deduplicate COMMUNITY() macro in the Intel pin control drivers
* Switch Freescale GPIO driver to use fwnode instead of of_node
* Miscellaneous clenups here and there

The following is an automated git shortlog grouped by driver:

alderlake:
 -  Deduplicate COMMUNITY macro code

cannonlake:
 -  Deduplicate COMMUNITY macro code

device property:
 -  Introduce fwnode_device_is_compatible() helper

icelake:
 -  Deduplicate COMMUNITY macro code

intel:
 -  Add Intel Moorefield pin controller support
 -  Use temporary variable for struct device
 -  Use str_enable_disable() helper

merrifield:
 -  Use temporary variable for struct device

qcom:
 -  lpass-lpi: Add missed bitfield.h

soc:
 -  fsl: qe: Switch to use fwnode instead of of_node

sunrisepoint:
 -  Deduplicate COMMUNITY macro code

tigerlake:
 -  Deduplicate COMMUNITY macro code
parents 196270c5 b14ef613

drivers/pinctrl/intel/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -47,6 +47,17 @@ config PINCTRL_MERRIFIELD 
	  interface that allows configuring of SoC pins and using them as

	  GPIOs.



config PINCTRL_MOOREFIELD

	tristate "Intel Moorefield pinctrl driver"

	depends on X86_INTEL_MID

	select PINMUX

	select PINCONF

	select GENERIC_PINCONF

	help

	  Moorefield Family-Level Interface Shim (FLIS) driver provides an

	  interface that allows configuring of SoC pins and using them as

	  GPIOs.



config PINCTRL_INTEL

	tristate

	select PINMUX

drivers/pinctrl/intel/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o 
obj-$(CONFIG_PINCTRL_CHERRYVIEW)	+= pinctrl-cherryview.o

obj-$(CONFIG_PINCTRL_LYNXPOINT)		+= pinctrl-lynxpoint.o

obj-$(CONFIG_PINCTRL_MERRIFIELD)	+= pinctrl-merrifield.o

obj-$(CONFIG_PINCTRL_MOOREFIELD)	+= pinctrl-moorefield.o

obj-$(CONFIG_PINCTRL_INTEL)		+= pinctrl-intel.o

obj-$(CONFIG_PINCTRL_ALDERLAKE)		+= pinctrl-alderlake.o

obj-$(CONFIG_PINCTRL_BROXTON)		+= pinctrl-broxton.o

drivers/pinctrl/intel/pinctrl-alderlake.c

+16 −24
Original line number Diff line number Diff line
@@ -34,33 +34,25 @@ 
		.gpio_base = (g),			\

	}



#define ADL_N_COMMUNITY(b, s, e, g)			\

#define ADL_COMMUNITY(b, s, e, g, v)				\

	{							\

		.barno = (b),					\

		.padown_offset = ADL_N_PAD_OWN,		\

		.padcfglock_offset = ADL_N_PADCFGLOCK,	\

		.hostown_offset = ADL_N_HOSTSW_OWN,	\

		.is_offset = ADL_N_GPI_IS,		\

		.ie_offset = ADL_N_GPI_IE,		\

		.padown_offset = ADL_##v##_PAD_OWN,		\

		.padcfglock_offset = ADL_##v##_PADCFGLOCK,	\

		.hostown_offset = ADL_##v##_HOSTSW_OWN,		\

		.is_offset = ADL_##v##_GPI_IS,			\

		.ie_offset = ADL_##v##_GPI_IE,			\

		.pin_base = (s),				\

		.npins = ((e) - (s) + 1),			\

		.gpps = (g),					\

		.ngpps = ARRAY_SIZE(g),				\

	}



#define ADL_N_COMMUNITY(b, s, e, g)			\

	ADL_COMMUNITY(b, s, e, g, N)



#define ADL_S_COMMUNITY(b, s, e, g)			\

	{						\

		.barno = (b),				\

		.padown_offset = ADL_S_PAD_OWN,		\

		.padcfglock_offset = ADL_S_PADCFGLOCK,	\

		.hostown_offset = ADL_S_HOSTSW_OWN,	\

		.is_offset = ADL_S_GPI_IS,		\

		.ie_offset = ADL_S_GPI_IE,		\

		.pin_base = (s),			\

		.npins = ((e) - (s) + 1),		\

		.gpps = (g),				\

		.ngpps = ARRAY_SIZE(g),			\

	}

	ADL_COMMUNITY(b, s, e, g, S)



/* Alder Lake-N */

static const struct pinctrl_pin_desc adln_pins[] = {

drivers/pinctrl/intel/pinctrl-cannonlake.c

+4 −4
Original line number Diff line number Diff line
@@ -30,12 +30,12 @@ 
		.gpio_base = (g),			\

	}



#define CNL_COMMUNITY(b, s, e, ho, g)			\

#define CNL_COMMUNITY(b, s, e, g, v)			\

	{						\

		.barno = (b),				\

		.padown_offset = CNL_PAD_OWN,		\

		.padcfglock_offset = CNL_PADCFGLOCK,	\

		.hostown_offset = (ho),			\

		.hostown_offset = CNL_##v##_HOSTSW_OWN,	\

		.is_offset = CNL_GPI_IS,		\

		.ie_offset = CNL_GPI_IE,		\

		.pin_base = (s),			\
@@ -45,10 +45,10 @@ 
	}



#define CNL_LP_COMMUNITY(b, s, e, g)			\

	CNL_COMMUNITY(b, s, e, CNL_LP_HOSTSW_OWN, g)

	CNL_COMMUNITY(b, s, e, g, LP)



#define CNL_H_COMMUNITY(b, s, e, g)			\

	CNL_COMMUNITY(b, s, e, CNL_H_HOSTSW_OWN, g)

	CNL_COMMUNITY(b, s, e, g, H)



/* Cannon Lake-H */

static const struct pinctrl_pin_desc cnlh_pins[] = {

drivers/pinctrl/intel/pinctrl-icelake.c

+4 −4
Original line number Diff line number Diff line
@@ -30,14 +30,14 @@ 
		.gpio_base = (g),			\

	}



#define ICL_COMMUNITY(b, s, e, ie, g)			\

#define ICL_COMMUNITY(b, s, e, g, v)			\

	{						\

		.barno = (b),				\

		.padown_offset = ICL_PAD_OWN,		\

		.padcfglock_offset = ICL_PADCFGLOCK,	\

		.hostown_offset = ICL_HOSTSW_OWN,	\

		.is_offset = ICL_GPI_IS,		\

		.ie_offset = (ie),			\

		.ie_offset = ICL_##v##_GPI_IE,		\

		.pin_base = (s),			\

		.npins = ((e) - (s) + 1),		\

		.gpps = (g),				\
@@ -45,10 +45,10 @@ 
	}



#define ICL_LP_COMMUNITY(b, s, e, g)			\

	ICL_COMMUNITY(b, s, e, ICL_LP_GPI_IE, g)

	ICL_COMMUNITY(b, s, e, g, LP)



#define ICL_N_COMMUNITY(b, s, e, g)			\

	ICL_COMMUNITY(b, s, e, ICL_N_GPI_IE, g)

	ICL_COMMUNITY(b, s, e, g, N)



/* Ice Lake-LP */

static const struct pinctrl_pin_desc icllp_pins[] = {