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Commit 94c3847d authored by Marcel Ziswiler's avatar Marcel Ziswiler Committed by Thierry Reding
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ARM: tegra: apalis-tk1: get rid of fake clocks simple bus 



Get rid of the fake clocks simple bus and use node names as per the
actual schematics.

Signed-off-by: default avatarMarcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 26e19cdf
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