drm/amdgpu: update UMC 6.1 RAS error counter register access path
use proper method for SMN register access Reviewed-by:Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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