Commit 98a90f1f authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: use the same HDP flush registers for all nbio 2.3.x 



Align RDNA2.x with other asics.  One HDP bit per SDMA instance,
aligned with firmware.  This is effectively a revert of
commit 369b7d04 ("drm/amdgpu/nbio2.3: don't use GPU_HDP_FLUSH bit 12").
On further discussions with the relevant hardware teams,
re-align the bits for SDMA.

Fixes: 369b7d04 ("drm/amdgpu/nbio2.3: don't use GPU_HDP_FLUSH bit 12")
Reviewed-by: default avatarKent Russell <kent.russell@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 912db6a5

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

+1 −4
Original line number Diff line number Diff line
@@ -2222,15 +2222,12 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(2, 3, 0):

	case IP_VERSION(2, 3, 1):

	case IP_VERSION(2, 3, 2):

		adev->nbio.funcs = &nbio_v2_3_funcs;

		adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;

		break;

	case IP_VERSION(3, 3, 0):

	case IP_VERSION(3, 3, 1):

	case IP_VERSION(3, 3, 2):

	case IP_VERSION(3, 3, 3):

		adev->nbio.funcs = &nbio_v2_3_funcs;

		adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc;

		adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;

		break;

	case IP_VERSION(4, 3, 0):

	case IP_VERSION(4, 3, 1):

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

+0 −21
Original line number Diff line number Diff line
@@ -328,27 +328,6 @@ const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg = { 
	.ref_and_mask_sdma1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK,

};



const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg_sc = {

	.ref_and_mask_cp0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK,

	.ref_and_mask_cp1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK,

	.ref_and_mask_cp2 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK,

	.ref_and_mask_cp3 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK,

	.ref_and_mask_cp4 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK,

	.ref_and_mask_cp5 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK,

	.ref_and_mask_cp6 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK,

	.ref_and_mask_cp7 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK,

	.ref_and_mask_cp8 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK,

	.ref_and_mask_cp9 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK,

	.ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK,

	.ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK,

	.ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK,

	.ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK,

	.ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK,

	.ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK,

	.ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK,

	.ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK,

};



static void nbio_v2_3_init_registers(struct amdgpu_device *adev)

{

	uint32_t def, data;

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h

+0 −1
Original line number Diff line number Diff line
@@ -27,7 +27,6 @@ 
#include "soc15_common.h"



extern const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg;

extern const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg_sc;

extern const struct amdgpu_nbio_funcs nbio_v2_3_funcs;



#endif