Commit 9b1b1b74 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2023-08-11' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "This week's fixes, as expected amdgpu is probably a little larger
  since it skipped a week, but otherwise a few nouveau fixes, a couple
  of bridge, rockchip and ivpu fixes.

  amdgpu:
   - S/G display workaround for platforms with >= 64G of memory
   - S0i3 fix
   - SMU 13.0.0 fixes
   - Disable SMU 13.x OD features temporarily while the interface is
     reworked to enable additional functionality
   - Fix cursor gamma issues on DCN3+
   - SMU 13.0.6 fixes
   - Fix possible UAF in CS IOCTL
   - Polaris display regression fix
   - Only enable CP GFX shadowing on SR-IOV

  amdkfd:
   - Raven/Picasso KFD regression fix

  bridge:
   - it6505: runtime PM fix
   - lt9611: revert Do not generate HFP/HBP/HSA and EOT packet

  nouveau:
   - enable global memory loads for helper invocations for userspace
     driver
   - dp 1.3 dpcd+ workaround fix
   - remove unused function
   - revert incorrect NULL check

  accel/ivpu:
   - Add set_pages_array_wc/uc for internal buffers

  rockchip:
   - Don't spam logs in atomic check"

* tag 'drm-fixes-2023-08-11' of git://anongit.freedesktop.org/drm/drm: (23 commits)
  drm/shmem-helper: Reset vma->vm_ops before calling dma_buf_mmap()
  drm/amdkfd: disable IOMMUv2 support for Raven
  drm/amdkfd: disable IOMMUv2 support for KV/CZ
  drm/amdkfd: ignore crat by default
  drm/amdgpu/gfx11: only enable CP GFX shadowing on SR-IOV
  drm/amd/display: Fix a regression on Polaris cards
  drm/amdgpu: fix possible UAF in amdgpu_cs_pass1()
  drm/amd/pm: Fix SMU v13.0.6 energy reporting
  drm/amd/display: check attr flag before set cursor degamma on DCN3+
  drm/amd/pm: disable the SMU13 OD feature support temporarily
  drm/amd/pm: correct the pcie width for smu 13.0.0
  drm/amd/display: Don't show stack trace for missing eDP
  drm/amdgpu: Match against exact bootloader status
  drm/amd/pm: skip the RLC stop when S0i3 suspend for SMU v13.0.4/11
  drm/amd: Disable S/G for APUs when 64GB or more host memory
  drm/rockchip: Don't spam logs in atomic check
  accel/ivpu: Add set_pages_array_wc/uc for internal buffers
  drm/nouveau/disp: Revert a NULL check inside nouveau_connector_get_modes
  Revert "drm/bridge: lt9611: Do not generate HFP/HBP/HSA and EOT packet"
  drm/nouveau: remove unused tu102_gr_load() function
  ...
parents 25aa0beb fbe8ff72

drivers/accel/ivpu/ivpu_gem.c

+8 −0
Original line number Original line Diff line number Diff line
@@ -173,6 +173,9 @@ static void internal_free_pages_locked(struct ivpu_bo *bo) 
{

{

	unsigned int i, npages = bo->base.size >> PAGE_SHIFT;

	unsigned int i, npages = bo->base.size >> PAGE_SHIFT;





	if (ivpu_bo_cache_mode(bo) != DRM_IVPU_BO_CACHED)

		set_pages_array_wb(bo->pages, bo->base.size >> PAGE_SHIFT);



	for (i = 0; i < npages; i++)

	for (i = 0; i < npages; i++)

		put_page(bo->pages[i]);

		put_page(bo->pages[i]);
@@ -587,6 +590,11 @@ ivpu_bo_alloc_internal(struct ivpu_device *vdev, u64 vpu_addr, u64 size, u32 fla 
	if (ivpu_bo_cache_mode(bo) != DRM_IVPU_BO_CACHED)

	if (ivpu_bo_cache_mode(bo) != DRM_IVPU_BO_CACHED)

		drm_clflush_pages(bo->pages, bo->base.size >> PAGE_SHIFT);

		drm_clflush_pages(bo->pages, bo->base.size >> PAGE_SHIFT);





	if (bo->flags & DRM_IVPU_BO_WC)

		set_pages_array_wc(bo->pages, bo->base.size >> PAGE_SHIFT);

	else if (bo->flags & DRM_IVPU_BO_UNCACHED)

		set_pages_array_uc(bo->pages, bo->base.size >> PAGE_SHIFT);



	prot = ivpu_bo_pgprot(bo, PAGE_KERNEL);

	prot = ivpu_bo_pgprot(bo, PAGE_KERNEL);

	bo->kvaddr = vmap(bo->pages, bo->base.size >> PAGE_SHIFT, VM_MAP, prot);

	bo->kvaddr = vmap(bo->pages, bo->base.size >> PAGE_SHIFT, VM_MAP, prot);

	if (!bo->kvaddr) {

	if (!bo->kvaddr) {

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -1296,6 +1296,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 
void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);

void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);

int amdgpu_device_pci_reset(struct amdgpu_device *adev);

int amdgpu_device_pci_reset(struct amdgpu_device *adev);

bool amdgpu_device_need_post(struct amdgpu_device *adev);

bool amdgpu_device_need_post(struct amdgpu_device *adev);

bool amdgpu_sg_display_supported(struct amdgpu_device *adev);

bool amdgpu_device_pcie_dynamic_switching_supported(void);

bool amdgpu_device_pcie_dynamic_switching_supported(void);

bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);

bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);

bool amdgpu_device_aspm_support_quirk(void);

bool amdgpu_device_aspm_support_quirk(void);

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -295,7 +295,7 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p, 




	if (!p->gang_size) {

	if (!p->gang_size) {

		ret = -EINVAL;

		ret = -EINVAL;

		goto free_partial_kdata;

		goto free_all_kdata;

	}

	}





	for (i = 0; i < p->gang_size; ++i) {

	for (i = 0; i < p->gang_size; ++i) {

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+26 −0
Original line number Original line Diff line number Diff line
@@ -1458,6 +1458,32 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev) 
	return true;

	return true;

}

}





/*

 * On APUs with >= 64GB white flickering has been observed w/ SG enabled.

 * Disable S/G on such systems until we have a proper fix.

 * https://gitlab.freedesktop.org/drm/amd/-/issues/2354

 * https://gitlab.freedesktop.org/drm/amd/-/issues/2735

 */

bool amdgpu_sg_display_supported(struct amdgpu_device *adev)

{

	switch (amdgpu_sg_display) {

	case -1:

		break;

	case 0:

		return false;

	case 1:

		return true;

	default:

		return false;

	}

	if ((totalram_pages() << (PAGE_SHIFT - 10)) +

	    (adev->gmc.real_vram_size / 1024) >= 64000000) {

		DRM_WARN("Disabling S/G due to >=64GB RAM\n");

		return false;

	}

	return true;

}



/*

/*

 * Intel hosts such as Raptor Lake and Sapphire Rapids don't support dynamic

 * Intel hosts such as Raptor Lake and Sapphire Rapids don't support dynamic

 * speed switching. Until we have confirmation from Intel that a specific host

 * speed switching. Until we have confirmation from Intel that a specific host

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+6 −2
Original line number Original line Diff line number Diff line
@@ -471,8 +471,12 @@ static void gfx_v11_0_check_fw_cp_gfx_shadow(struct amdgpu_device *adev) 
	case IP_VERSION(11, 0, 3):

	case IP_VERSION(11, 0, 3):

		if ((adev->gfx.me_fw_version >= 1505) &&

		if ((adev->gfx.me_fw_version >= 1505) &&

		    (adev->gfx.pfp_fw_version >= 1600) &&

		    (adev->gfx.pfp_fw_version >= 1600) &&

		    (adev->gfx.mec_fw_version >= 512))

		    (adev->gfx.mec_fw_version >= 512)) {

			if (amdgpu_sriov_vf(adev))

				adev->gfx.cp_gfx_shadow = true;

				adev->gfx.cp_gfx_shadow = true;

			else

				adev->gfx.cp_gfx_shadow = false;

		}

		break;

		break;

	default:

	default:

		adev->gfx.cp_gfx_shadow = false;

		adev->gfx.cp_gfx_shadow = false;