Commit 9e7f2588 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'edac_updates_for_v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras

Pull EDAC updates from Borislav Petkov:
 "Somewhat busier than usual this cycle:

   - Add support for AST2400 and AST2600 hw to aspeed_edac (Troy Lee)

   - Remove an orphaned mv64x60_edac driver. Good riddance (Michael
     Ellerman)

   - Add a new igen6 driver for Intel client SoCs with an integrated
     memory controller and using in-band ECC (Qiuxu Zhuo and Tony Luck)

   - The usual smattering of fixes and cleanups all over"

* tag 'edac_updates_for_v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras:
  EDAC/mv64x60: Remove orphan mv64x60 driver
  EDAC/aspeed: Add support for AST2400 and AST2600
  ARM: dts: aspeed: Add AST2600 EDAC into common devicetree
  dt-bindings: edac: aspeed-sdram-edac: Add ast2400/ast2600 support
  EDAC/amd64: Fix PCI component registration
  EDAC/igen6: ecclog_llist can be static
  EDAC/i10nm: Add Intel Sapphire Rapids server support
  EDAC: Add DDR5 new memory type
  EDAC/i10nm: Use readl() to access MMIO registers
  MAINTAINERS: Add entry for Intel IGEN6 EDAC driver
  EDAC/igen6: Add debugfs interface for Intel client SoC EDAC driver
  EDAC/igen6: Add EDAC driver for Intel client SoCs using IBECC
  EDAC/synopsys: Return the correct value in mc_probe()
  MAINTAINERS: Clean up the F: entries for some EDAC drivers
  EDAC: Add three new memory types
  EDAC: Fix some kernel-doc markups
  EDAC: Do not issue useless debug statements in the polling routine
  EDAC/amd64: Remove unneeded breaks
parents 9e4b0d55 f84b7999
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+6 −3
Original line number Diff line number Diff line
Aspeed AST2500 SoC EDAC node
Aspeed BMC SoC EDAC node

The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error
The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
correction check).

The memory controller supports SECDED (single bit error correction, double bit
@@ -11,7 +11,10 @@ Note, the bootloader must configure ECC mode in the memory controller.


Required properties:
- compatible: should be "aspeed,ast2500-sdram-edac"
- compatible: should be one of
	- "aspeed,ast2400-sdram-edac"
	- "aspeed,ast2500-sdram-edac"
	- "aspeed,ast2600-sdram-edac"
- reg:        sdram controller register set should be <0x1e6e0000 0x174>
- interrupts: should be AVIC interrupt #0

+9 −2
Original line number Diff line number Diff line
@@ -2485,7 +2485,7 @@ F: drivers/clk/socfpga/
ARM/SOCFPGA EDAC SUPPORT
M:	Dinh Nguyen <dinguyen@kernel.org>
S:	Maintained
F:	drivers/edac/altera_edac.
F:	drivers/edac/altera_edac.[ch]
ARM/SPREADTRUM SoC SUPPORT
M:	Orson Zhai <orsonzhai@gmail.com>
@@ -6370,6 +6370,13 @@ L: linux-edac@vger.kernel.org
S:	Maintained
F:	drivers/edac/ie31200_edac.c
EDAC-IGEN6
M:	Tony Luck <tony.luck@intel.com>
R:	Qiuxu Zhuo <qiuxu.zhuo@intel.com>
L:	linux-edac@vger.kernel.org
S:	Maintained
F:	drivers/edac/igen6_edac.c
EDAC-MPC85XX
M:	Johannes Thumshirn <morbidrsa@gmail.com>
L:	linux-edac@vger.kernel.org
@@ -6419,7 +6426,7 @@ EDAC-SKYLAKE
M:	Tony Luck <tony.luck@intel.com>
L:	linux-edac@vger.kernel.org
S:	Maintained
F:	drivers/edac/skx_*.c
F:	drivers/edac/skx_*.[ch]
EDAC-TI
M:	Tero Kristo <t-kristo@ti.com>
+6 −0
Original line number Diff line number Diff line
@@ -69,6 +69,12 @@ timer {
		always-on;
	};

	edac: sdram@1e6e0000 {
		compatible = "aspeed,ast2600-sdram-edac", "syscon";
		reg = <0x1e6e0000 0x174>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	};

	ahb {
		compatible = "simple-bus";
		#address-cells = <1>;
+12 −10
Original line number Diff line number Diff line
@@ -269,6 +269,15 @@ config EDAC_PND2
	  first used on the Apollo Lake platform and Denverton
	  micro-server but may appear on others in the future.

config EDAC_IGEN6
	tristate "Intel client SoC Integrated MC"
	depends on PCI && X86_64 && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG
	help
	  Support for error detection and correction on the Intel
	  client SoC Integrated Memory Controller using In-Band ECC IP.
	  This In-Band ECC is first used on the Elkhart Lake SoC but
	  may appear on others in the future.

config EDAC_MPC85XX
	bool "Freescale MPC83xx / MPC85xx"
	depends on FSL_SOC && EDAC=y
@@ -283,13 +292,6 @@ config EDAC_LAYERSCAPE
	  Support for error detection and correction on Freescale memory
	  controllers on Layerscape SoCs.

config EDAC_MV64X60
	tristate "Marvell MV64x60"
	depends on MV64X60
	help
	  Support for error detection and correction on the Marvell
	  MV64360 and MV64460 chipsets.

config EDAC_PASEMI
	tristate "PA Semi PWRficient"
	depends on PPC_PASEMI && PCI
@@ -515,10 +517,10 @@ config EDAC_QCOM
	  health, you should probably say 'Y' here.

config EDAC_ASPEED
	tristate "Aspeed AST 2500 SoC"
	depends on MACH_ASPEED_G5
	tristate "Aspeed AST BMC SoC"
	depends on ARCH_ASPEED
	help
	  Support for error detection and correction on the Aspeed AST 2500 SoC.
	  Support for error detection and correction on the Aspeed AST BMC SoC.

	  First, ECC must be configured in the bootloader. Then, this driver
	  will expose error counters via the EDAC kernel framework.
+1 −1
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ obj-$(CONFIG_EDAC_I7300) += i7300_edac.o
obj-$(CONFIG_EDAC_I7CORE)		+= i7core_edac.o
obj-$(CONFIG_EDAC_SBRIDGE)		+= sb_edac.o
obj-$(CONFIG_EDAC_PND2)			+= pnd2_edac.o
obj-$(CONFIG_EDAC_IGEN6)			+= igen6_edac.o
obj-$(CONFIG_EDAC_E7XXX)		+= e7xxx_edac.o
obj-$(CONFIG_EDAC_E752X)		+= e752x_edac.o
obj-$(CONFIG_EDAC_I82443BXGX)		+= i82443bxgx_edac.o
@@ -64,7 +65,6 @@ obj-$(CONFIG_EDAC_SKX) += skx_edac.o
i10nm_edac-y				:= skx_common.o i10nm_base.o
obj-$(CONFIG_EDAC_I10NM)		+= i10nm_edac.o

obj-$(CONFIG_EDAC_MV64X60)		+= mv64x60_edac.o
obj-$(CONFIG_EDAC_CELL)			+= cell_edac.o
obj-$(CONFIG_EDAC_PPC4XX)		+= ppc4xx_edac.o
obj-$(CONFIG_EDAC_AMD8111)		+= amd8111_edac.o
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