drm/amd/display: Raise DPG height during timing synchronization

[Why]
Underflow counter increases in AGM when performing some mode switches due
to timing sync, which is a known hardware issue.

[How]
Temporarily raise DPG height during timing sync so that underflow is not
reported.

Signed-off-by: Taimur Hassan <syed.hassan@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>