arm64: dts: imx8mp: Improve bluetooth UART on DH electronics i.MX8M Plus DHCOM

Use PLL1_80M instead of PLL3 to drive UART2 clock divided down to 80 MHz
instead of 64 MHz to obtain suitable block clock for exact 4 Mbdps, which
is the maximum supported baud rate by the muRata 2AE BT UART.

The difference here is that at 64 MHz UART block clock, the clock with are
divided by 16 (due to oversampling) to 4 MHz and the baud rate generator
then needs to be set to UBIR+1/UBMR+1 = 1/1 to yield 4 Mbdps . In case of
80 MHz UART block clock divided by 16 to 5 MHz, the baud rate generator
needs to be set to UBIR+1/UBMR+1 = 4/5 to yield 4 Mbdps .

Both options are valid and yield the same result, except using the PLL1_80M
output requires fewer clock tree changes, since the PLL1 already generates
the 80 MHz usable for UART, which frees the PLL3 for other uses.

Suggested-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>