Commit afdecb23 authored by Matt Atwood's avatar Matt Atwood Committed by Rodrigo Vivi
Browse files

drm/i915/dg2: Introduce Wa_18019271663 



Wa_18019271663 applies to all DG2 steppings and skus.

Bspec: 66622

Signed-off-by: default avatarMatt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221123183648.407058-2-matthew.s.atwood@intel.com


(cherry picked from commit 900a80c5)
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent ce38cb84

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+4 −3
Original line number Original line Diff line number Diff line
@@ -429,9 +429,10 @@ 
#define   RC_OP_FLUSH_ENABLE			(1 << 0)

#define   RC_OP_FLUSH_ENABLE			(1 << 0)

#define   HIZ_RAW_STALL_OPT_DISABLE		(1 << 2)

#define   HIZ_RAW_STALL_OPT_DISABLE		(1 << 2)

#define CACHE_MODE_1				_MMIO(0x7004) /* IVB+ */

#define CACHE_MODE_1				_MMIO(0x7004) /* IVB+ */

#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE	(1 << 6)

#define   MSAA_OPTIMIZATION_REDUC_DISABLE	REG_BIT(11)

#define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1 << 6)

#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE	REG_BIT(6)

#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	(1 << 1)

#define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	REG_BIT(6)

#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	REG_BIT(1)





#define GEN7_GT_MODE				_MMIO(0x7008)

#define GEN7_GT_MODE				_MMIO(0x7008)

#define   GEN9_IZ_HASHING_MASK(slice)		(0x3 << ((slice) * 2))

#define   GEN9_IZ_HASHING_MASK(slice)		(0x3 << ((slice) * 2))

drivers/gpu/drm/i915/gt/intel_workarounds.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -781,6 +781,9 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, 




	/* Wa_15010599737:dg2 */

	/* Wa_15010599737:dg2 */

	wa_mcr_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);

	wa_mcr_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);



	/* Wa_18019271663:dg2 */

	wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);

}

}





static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,

static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,