Commit b751ed04 authored by Paul Gortmaker's avatar Paul Gortmaker Committed by Michael Ellerman
Browse files

powerpc: drop MPC85xx_CDS platform support 



The MPC8541/8548/8555 Configurable Development System (CDS) were the
vehicle used to provide evaluation of the 1st e500-v2 CPUs around 2007.

Similar to the earlier MPC83xx-MDS systems we removed, the "brains"
exist on a PCI-X card, but additional connectors exist to the right of
the PCI-X slot, two structural metal pins are used to provide stability
in a vertical ATX mounting, and the CPU is now on a daughter-card vs. a
clamped down BGA.

Given the extra complexity and risk of connector damage, the 8548CDS
I had access to came pre-assembled in a basic white Antec case common
for that era, and I'm inclined to assume that was the default.

Power was typical "Pentium4" 2005 ATX - the main 20 pin connector went
to the PCI ATX form factor backplane, and the 4 pin black/yellow went
to the CPU card.

Like previous evaluation boards, they attempted to provide break-out
connectors for as many features as possible, and that made for a fairly
complex looking system.

In any case, these are over 15 years old, and fairly complex systems,
originally made for a small group of industry related people, and made
for use where quiet fan operation wasn't important.  Given that, it
makes sense to remove support from them in 2023.

Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://msgid.link/20230620043300.197546-3-paul.gortmaker@windriver.com
parent 384e338a

arch/powerpc/boot/Makefile

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Original line number Diff line number Diff line
@@ -342,9 +342,6 @@ image-$(CONFIG_MPC834x_ITX) += cuImage.mpc8349emitx \ 
image-$(CONFIG_ASP834x)			+= dtbImage.asp834x-redboot



# Board ports in arch/powerpc/platform/85xx/Kconfig

image-$(CONFIG_MPC85xx_CDS)		+= cuImage.mpc8541cds \

					   cuImage.mpc8548cds_32b \

					   cuImage.mpc8555cds

image-$(CONFIG_MPC85xx_MDS)		+= cuImage.mpc8568mds

image-$(CONFIG_MPC85xx_DS)		+= cuImage.mpc8544ds \

					   cuImage.mpc8572ds

arch/powerpc/boot/dts/fsl/mpc8541cds.dts

deleted100644 → 0
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Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-or-later

/*

 * MPC8541 CDS Device Tree Source

 *

 * Copyright 2006, 2008 Freescale Semiconductor Inc.

 */



/dts-v1/;



/include/ "e500v1_power_isa.dtsi"



/ {

	model = "MPC8541CDS";

	compatible = "MPC8541CDS", "MPC85xxCDS";

	#address-cells = <1>;

	#size-cells = <1>;



	aliases {

		ethernet0 = &enet0;

		ethernet1 = &enet1;

		serial0 = &serial0;

		serial1 = &serial1;

		pci0 = &pci0;

		pci1 = &pci1;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		PowerPC,8541@0 {

			device_type = "cpu";

			reg = <0x0>;

			d-cache-line-size = <32>;	// 32 bytes

			i-cache-line-size = <32>;	// 32 bytes

			d-cache-size = <0x8000>;		// L1, 32K

			i-cache-size = <0x8000>;		// L1, 32K

			timebase-frequency = <0>;	//  33 MHz, from uboot

			bus-frequency = <0>;	// 166 MHz

			clock-frequency = <0>;	// 825 MHz, from uboot

			next-level-cache = <&L2>;

		};

	};



	memory {

		device_type = "memory";

		reg = <0x0 0x8000000>;	// 128M at 0x0

	};



	soc8541@e0000000 {

		#address-cells = <1>;

		#size-cells = <1>;

		device_type = "soc";

		compatible = "simple-bus";

		ranges = <0x0 0xe0000000 0x100000>;

		bus-frequency = <0>;



		ecm-law@0 {

			compatible = "fsl,ecm-law";

			reg = <0x0 0x1000>;

			fsl,num-laws = <8>;

		};



		ecm@1000 {

			compatible = "fsl,mpc8541-ecm", "fsl,ecm";

			reg = <0x1000 0x1000>;

			interrupts = <17 2>;

			interrupt-parent = <&mpic>;

		};



		memory-controller@2000 {

			compatible = "fsl,mpc8541-memory-controller";

			reg = <0x2000 0x1000>;

			interrupt-parent = <&mpic>;

			interrupts = <18 2>;

		};



		L2: l2-cache-controller@20000 {

			compatible = "fsl,mpc8541-l2-cache-controller";

			reg = <0x20000 0x1000>;

			cache-line-size = <32>;	// 32 bytes

			cache-size = <0x40000>;	// L2, 256K

			interrupt-parent = <&mpic>;

			interrupts = <16 2>;

		};



		i2c@3000 {

			#address-cells = <1>;

			#size-cells = <0>;

			cell-index = <0>;

			compatible = "fsl-i2c";

			reg = <0x3000 0x100>;

			interrupts = <43 2>;

			interrupt-parent = <&mpic>;

			dfsrr;

		};



		dma@21300 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma";

			reg = <0x21300 0x4>;

			ranges = <0x0 0x21100 0x200>;

			cell-index = <0>;

			dma-channel@0 {

				compatible = "fsl,mpc8541-dma-channel",

						"fsl,eloplus-dma-channel";

				reg = <0x0 0x80>;

				cell-index = <0>;

				interrupt-parent = <&mpic>;

				interrupts = <20 2>;

			};

			dma-channel@80 {

				compatible = "fsl,mpc8541-dma-channel",

						"fsl,eloplus-dma-channel";

				reg = <0x80 0x80>;

				cell-index = <1>;

				interrupt-parent = <&mpic>;

				interrupts = <21 2>;

			};

			dma-channel@100 {

				compatible = "fsl,mpc8541-dma-channel",

						"fsl,eloplus-dma-channel";

				reg = <0x100 0x80>;

				cell-index = <2>;

				interrupt-parent = <&mpic>;

				interrupts = <22 2>;

			};

			dma-channel@180 {

				compatible = "fsl,mpc8541-dma-channel",

						"fsl,eloplus-dma-channel";

				reg = <0x180 0x80>;

				cell-index = <3>;

				interrupt-parent = <&mpic>;

				interrupts = <23 2>;

			};

		};



		enet0: ethernet@24000 {

			#address-cells = <1>;

			#size-cells = <1>;

			cell-index = <0>;

			device_type = "network";

			model = "TSEC";

			compatible = "gianfar";

			reg = <0x24000 0x1000>;

			ranges = <0x0 0x24000 0x1000>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			interrupts = <29 2 30 2 34 2>;

			interrupt-parent = <&mpic>;

			tbi-handle = <&tbi0>;

			phy-handle = <&phy0>;



			mdio@520 {

				#address-cells = <1>;

				#size-cells = <0>;

				compatible = "fsl,gianfar-mdio";

				reg = <0x520 0x20>;



				phy0: ethernet-phy@0 {

					interrupt-parent = <&mpic>;

					interrupts = <5 1>;

					reg = <0x0>;

				};

				phy1: ethernet-phy@1 {

					interrupt-parent = <&mpic>;

					interrupts = <5 1>;

					reg = <0x1>;

				};

				tbi0: tbi-phy@11 {

					reg = <0x11>;

					device_type = "tbi-phy";

				};

			};

		};



		enet1: ethernet@25000 {

			#address-cells = <1>;

			#size-cells = <1>;

			cell-index = <1>;

			device_type = "network";

			model = "TSEC";

			compatible = "gianfar";

			reg = <0x25000 0x1000>;

			ranges = <0x0 0x25000 0x1000>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			interrupts = <35 2 36 2 40 2>;

			interrupt-parent = <&mpic>;

			tbi-handle = <&tbi1>;

			phy-handle = <&phy1>;



			mdio@520 {

				#address-cells = <1>;

				#size-cells = <0>;

				compatible = "fsl,gianfar-tbi";

				reg = <0x520 0x20>;



				tbi1: tbi-phy@11 {

					reg = <0x11>;

					device_type = "tbi-phy";

				};

			};

		};



		serial0: serial@4500 {

			cell-index = <0>;

			device_type = "serial";

			compatible = "fsl,ns16550", "ns16550";

			reg = <0x4500 0x100>; 	// reg base, size

			clock-frequency = <0>; 	// should we fill in in uboot?

			interrupts = <42 2>;

			interrupt-parent = <&mpic>;

		};



		serial1: serial@4600 {

			cell-index = <1>;

			device_type = "serial";

			compatible = "fsl,ns16550", "ns16550";

			reg = <0x4600 0x100>;	// reg base, size

			clock-frequency = <0>; 	// should we fill in in uboot?

			interrupts = <42 2>;

			interrupt-parent = <&mpic>;

		};



		crypto@30000 {

			compatible = "fsl,sec2.0";

			reg = <0x30000 0x10000>;

			interrupts = <45 2>;

			interrupt-parent = <&mpic>;

			fsl,num-channels = <4>;

			fsl,channel-fifo-len = <24>;

			fsl,exec-units-mask = <0x7e>;

			fsl,descriptor-types-mask = <0x01010ebf>;

		};



		mpic: pic@40000 {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <2>;

			reg = <0x40000 0x40000>;

			compatible = "chrp,open-pic";

			device_type = "open-pic";

		};



		cpm@919c0 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "fsl,mpc8541-cpm", "fsl,cpm2";

			reg = <0x919c0 0x30>;

			ranges;



			muram@80000 {

				#address-cells = <1>;

				#size-cells = <1>;

				ranges = <0x0 0x80000 0x10000>;



				data@0 {

					compatible = "fsl,cpm-muram-data";

					reg = <0x0 0x2000 0x9000 0x1000>;

				};

			};



			brg@919f0 {

				compatible = "fsl,mpc8541-brg",

				             "fsl,cpm2-brg",

				             "fsl,cpm-brg";

				reg = <0x919f0 0x10 0x915f0 0x10>;

			};



			cpmpic: pic@90c00 {

				interrupt-controller;

				#address-cells = <0>;

				#interrupt-cells = <2>;

				interrupts = <46 2>;

				interrupt-parent = <&mpic>;

				reg = <0x90c00 0x80>;

				compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";

			};

		};

	};



	pci0: pci@e0008000 {

		interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;

		interrupt-map = <



			/* IDSEL 0x10 */

			0x8000 0x0 0x0 0x1 &mpic 0x0 0x1

			0x8000 0x0 0x0 0x2 &mpic 0x1 0x1

			0x8000 0x0 0x0 0x3 &mpic 0x2 0x1

			0x8000 0x0 0x0 0x4 &mpic 0x3 0x1



			/* IDSEL 0x11 */

			0x8800 0x0 0x0 0x1 &mpic 0x0 0x1

			0x8800 0x0 0x0 0x2 &mpic 0x1 0x1

			0x8800 0x0 0x0 0x3 &mpic 0x2 0x1

			0x8800 0x0 0x0 0x4 &mpic 0x3 0x1



			/* IDSEL 0x12 (Slot 1) */

			0x9000 0x0 0x0 0x1 &mpic 0x0 0x1

			0x9000 0x0 0x0 0x2 &mpic 0x1 0x1

			0x9000 0x0 0x0 0x3 &mpic 0x2 0x1

			0x9000 0x0 0x0 0x4 &mpic 0x3 0x1



			/* IDSEL 0x13 (Slot 2) */

			0x9800 0x0 0x0 0x1 &mpic 0x1 0x1

			0x9800 0x0 0x0 0x2 &mpic 0x2 0x1

			0x9800 0x0 0x0 0x3 &mpic 0x3 0x1

			0x9800 0x0 0x0 0x4 &mpic 0x0 0x1



			/* IDSEL 0x14 (Slot 3) */

			0xa000 0x0 0x0 0x1 &mpic 0x2 0x1

			0xa000 0x0 0x0 0x2 &mpic 0x3 0x1

			0xa000 0x0 0x0 0x3 &mpic 0x0 0x1

			0xa000 0x0 0x0 0x4 &mpic 0x1 0x1



			/* IDSEL 0x15 (Slot 4) */

			0xa800 0x0 0x0 0x1 &mpic 0x3 0x1

			0xa800 0x0 0x0 0x2 &mpic 0x0 0x1

			0xa800 0x0 0x0 0x3 &mpic 0x1 0x1

			0xa800 0x0 0x0 0x4 &mpic 0x2 0x1



			/* Bus 1 (Tundra Bridge) */

			/* IDSEL 0x12 (ISA bridge) */

			0x19000 0x0 0x0 0x1 &mpic 0x0 0x1

			0x19000 0x0 0x0 0x2 &mpic 0x1 0x1

			0x19000 0x0 0x0 0x3 &mpic 0x2 0x1

			0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;

		interrupt-parent = <&mpic>;

		interrupts = <24 2>;

		bus-range = <0 0>;

		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000

			  0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;

		clock-frequency = <66666666>;

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		reg = <0xe0008000 0x1000>;

		compatible = "fsl,mpc8540-pci";

		device_type = "pci";



		i8259@19000 {

			interrupt-controller;

			device_type = "interrupt-controller";

			reg = <0x19000 0x0 0x0 0x0 0x1>;

			#address-cells = <0>;

			#interrupt-cells = <2>;

			compatible = "chrp,iic";

			interrupts = <1>;

			interrupt-parent = <&pci0>;

		};

	};



	pci1: pci@e0009000 {

		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;

		interrupt-map = <



			/* IDSEL 0x15 */

			0xa800 0x0 0x0 0x1 &mpic 0xb 0x1

			0xa800 0x0 0x0 0x2 &mpic 0xb 0x1

			0xa800 0x0 0x0 0x3 &mpic 0xb 0x1

			0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;

		interrupt-parent = <&mpic>;

		interrupts = <25 2>;

		bus-range = <0 0>;

		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000

			  0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;

		clock-frequency = <66666666>;

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		reg = <0xe0009000 0x1000>;

		compatible = "fsl,mpc8540-pci";

		device_type = "pci";

	};

};

arch/powerpc/boot/dts/fsl/mpc8548cds.dtsi

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Original line number Diff line number Diff line 
/*

 * MPC8548CDS Device Tree Source stub (no addresses or top-level ranges)

 *

 * Copyright 2012 Freescale Semiconductor Inc.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:

 *     * Redistributions of source code must retain the above copyright

 *       notice, this list of conditions and the following disclaimer.

 *     * Redistributions in binary form must reproduce the above copyright

 *       notice, this list of conditions and the following disclaimer in the

 *       documentation and/or other materials provided with the distribution.

 *     * Neither the name of Freescale Semiconductor nor the

 *       names of its contributors may be used to endorse or promote products

 *       derived from this software without specific prior written permission.

 *

 *

 * ALTERNATIVELY, this software may be distributed under the terms of the

 * GNU General Public License ("GPL") as published by the Free Software

 * Foundation, either version 2 of that License or (at your option) any

 * later version.

 *

 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY

 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY

 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS

 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



&board_lbc {

	nor@0,0 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "cfi-flash";

		reg = <0x0 0x0 0x01000000>;

		bank-width = <2>;

		device-width = <2>;



		partition@0 {

			reg = <0x0 0x0b00000>;

			label = "ramdisk-nor";

		};



		partition@300000 {

			reg = <0x0b00000 0x0400000>;

			label = "kernel-nor";

		};



		partition@700000 {

			reg = <0x0f00000 0x060000>;

			label = "dtb-nor";

		};



		partition@760000 {

			reg = <0x0f60000 0x020000>;

			label = "env-nor";

			read-only;

		};



		partition@780000 {

			reg = <0x0f80000 0x080000>;

			label = "u-boot-nor";

			read-only;

		};

	};



	board-control@1,0 {

		compatible = "fsl,mpc8548cds-fpga";

		reg = <0x1 0x0 0x1000>;

	};

};



&board_soc {

	i2c@3000 {

		eeprom@50 {

			compatible = "atmel,24c64";

			reg = <0x50>;

		};



		eeprom@56 {

			compatible = "atmel,24c64";

			reg = <0x56>;

		};



		eeprom@57 {

			compatible = "atmel,24c64";

			reg = <0x57>;

		};

	};



	i2c@3100 {

		eeprom@50 {

			compatible = "atmel,24c64";

			reg = <0x50>;

		};

	};



	enet0: ethernet@24000 {

		tbi-handle = <&tbi0>;

		phy-handle = <&phy0>;

	};



	mdio@24520 {

		phy0: ethernet-phy@0 {

			interrupts = <5 1 0 0>;

			reg = <0x0>;

		};

		phy1: ethernet-phy@1 {

			interrupts = <5 1 0 0>;

			reg = <0x1>;

		};

		phy2: ethernet-phy@2 {

			interrupts = <5 1 0 0>;

			reg = <0x2>;

		};

		phy3: ethernet-phy@3 {

			interrupts = <5 1 0 0>;

			reg = <0x3>;

		};

		tbi0: tbi-phy@11 {

			reg = <0x11>;

			device_type = "tbi-phy";

		};

	};



	enet1: ethernet@25000 {

		tbi-handle = <&tbi1>;

		phy-handle = <&phy1>;

	};



	mdio@25520 {

		tbi1: tbi-phy@11 {

			reg = <0x11>;

			device_type = "tbi-phy";

		};

	};



	enet2: ethernet@26000 {

		tbi-handle = <&tbi2>;

		phy-handle = <&phy2>;

	};



	mdio@26520 {

		tbi2: tbi-phy@11 {

			reg = <0x11>;

			device_type = "tbi-phy";

		};

	};



	enet3: ethernet@27000 {

		tbi-handle = <&tbi3>;

		phy-handle = <&phy3>;

	};



	mdio@27520 {

		tbi3: tbi-phy@11 {

			reg = <0x11>;

			device_type = "tbi-phy";

		};

	};

};



&board_pci0 {

	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;

	interrupt-map = <

		/* IDSEL 0x4 (PCIX Slot 2) */

		0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0

		0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0

		0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0

		0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0



		/* IDSEL 0x5 (PCIX Slot 3) */

		0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0

		0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0

		0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0

		0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0



		/* IDSEL 0x6 (PCIX Slot 4) */

		0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0

		0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0

		0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0

		0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0



		/* IDSEL 0x8 (PCIX Slot 5) */

		0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0

		0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0

		0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0

		0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0



		/* IDSEL 0xC (Tsi310 bridge) */

		0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0

		0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0

		0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0

		0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0



		/* IDSEL 0x14 (Slot 2) */

		0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0

		0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0

		0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0

		0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0



		/* IDSEL 0x15 (Slot 3) */

		0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0

		0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0

		0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0

		0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0



		/* IDSEL 0x16 (Slot 4) */

		0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0

		0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0

		0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0

		0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0



		/* IDSEL 0x18 (Slot 5) */

		0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0

		0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0

		0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0

		0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0



		/* IDSEL 0x1C (Tsi310 bridge PCI primary) */

		0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0

		0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0

		0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0

		0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;



	pci_bridge@1c {

		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;

		interrupt-map = <



			/* IDSEL 0x00 (PrPMC Site) */

			0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0

			0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0

			0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0

			0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0



			/* IDSEL 0x04 (VIA chip) */

			0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0

			0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0

			0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0

			0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0



			/* IDSEL 0x05 (8139) */

			0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0



			/* IDSEL 0x06 (Slot 6) */

			0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0

			0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0

			0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0

			0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0



			/* IDESL 0x07 (Slot 7) */

			0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0

			0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0

			0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0

			0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;



		reg = <0xe000 0x0 0x0 0x0 0x0>;

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		ranges = <0x2000000 0x0 0x80000000

			  0x2000000 0x0 0x80000000

			  0x0 0x20000000

			  0x1000000 0x0 0x0

			  0x1000000 0x0 0x0

			  0x0 0x80000>;

		clock-frequency = <33333333>;



		isa@4 {

			device_type = "isa";

			#interrupt-cells = <2>;

			#size-cells = <1>;

			#address-cells = <2>;

			reg = <0x2000 0x0 0x0 0x0 0x0>;

			ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;

			interrupt-parent = <&i8259>;



			i8259: interrupt-controller@20 {

				interrupt-controller;

				device_type = "interrupt-controller";

				reg = <0x1 0x20 0x2

				       0x1 0xa0 0x2

				       0x1 0x4d0 0x2>;

				#address-cells = <0>;

				#interrupt-cells = <2>;

				compatible = "chrp,iic";

				interrupts = <0 1 0 0>;

				interrupt-parent = <&mpic>;

			};



			rtc@70 {

				compatible = "pnpPNP,b00";

				reg = <0x1 0x70 0x2>;

			};

		};

	};

};

arch/powerpc/boot/dts/fsl/mpc8548cds_32b.dts

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// SPDX-License-Identifier: GPL-2.0-or-later

/*

 * MPC8548 CDS Device Tree Source (32-bit address map)

 *

 * Copyright 2006, 2008, 2011-2012 Freescale Semiconductor Inc.

 */



/include/ "mpc8548si-pre.dtsi"



/ {

	model = "MPC8548CDS";

	compatible = "MPC8548CDS", "MPC85xxCDS";



	memory {

		device_type = "memory";

		reg = <0 0 0x0 0x8000000>;	// 128M at 0x0

	};



	board_lbc: lbc: localbus@e0005000 {

		reg = <0 0xe0005000 0 0x1000>;



		ranges = <0x0 0x0 0x0 0xff000000 0x01000000

			  0x1 0x0 0x0 0xf8004000 0x00001000>;



	};



	board_soc: soc: soc8548@e0000000 {

		ranges = <0 0x0 0xe0000000 0x100000>;

	};



	board_pci0: pci0: pci@e0008000 {

		reg = <0 0xe0008000 0 0x1000>;

		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000

			  0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;

		clock-frequency = <66666666>;

	};



	pci1: pci@e0009000 {

		reg = <0 0xe0009000 0 0x1000>;

		ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000

			  0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>;

		clock-frequency = <66666666>;

		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;

		interrupt-map = <



			/* IDSEL 0x15 */

			0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0

			0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0

			0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0

			0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;

	};



	pci2: pcie@e000a000 {

		reg = <0 0xe000a000 0 0x1000>;

		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000

			  0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>;

		pcie@0 {

			ranges = <0x2000000 0x0 0xa0000000

				  0x2000000 0x0 0xa0000000

				  0x0 0x20000000



				  0x1000000 0x0 0x0

				  0x1000000 0x0 0x0

				  0x0 0x100000>;

		};

	};



	rio: rapidio@e00c0000 {

		reg = <0x0 0xe00c0000 0x0 0x20000>;

		port1 {

			ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;

		};

	};

};



/*

 * mpc8548cds.dtsi must be last to ensure board_pci0 overrides pci0 settings

 * for interrupt-map & interrupt-map-mask.

 */



/include/ "mpc8548si-post.dtsi"

/include/ "mpc8548cds.dtsi"

arch/powerpc/boot/dts/fsl/mpc8548cds_36b.dts

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Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-or-later

/*

 * MPC8548 CDS Device Tree Source (36-bit address map)

 *

 * Copyright 2012 Freescale Semiconductor Inc.

 */



/include/ "mpc8548si-pre.dtsi"



/ {

	model = "MPC8548CDS";

	compatible = "MPC8548CDS", "MPC85xxCDS";



	memory {

		device_type = "memory";

		reg = <0 0 0x0 0x8000000>;	// 128M at 0x0

	};



	board_lbc: lbc: localbus@fe0005000 {

		reg = <0xf 0xe0005000 0 0x1000>;



		ranges = <0x0 0x0 0xf 0xff000000 0x01000000

			  0x1 0x0 0xf 0xf8004000 0x00001000>;



	};



	board_soc: soc: soc8548@fe0000000 {

		ranges = <0 0xf 0xe0000000 0x100000>;

	};



	board_pci0: pci0: pci@fe0008000 {

		reg = <0xf 0xe0008000 0 0x1000>;

		ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000

			  0x1000000 0x0 0x00000000 0xf 0xe2000000 0x0 0x800000>;

		clock-frequency = <66666666>;

	};



	pci1: pci@fe0009000 {

		reg = <0xf 0xe0009000 0 0x1000>;

		ranges = <0x2000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000

			  0x1000000 0x0 0x00000000 0xf 0xe2800000 0x0 0x800000>;

		clock-frequency = <66666666>;

		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;

		interrupt-map = <



			/* IDSEL 0x15 */

			0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0

			0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0

			0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0

			0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;

	};



	pci2: pcie@fe000a000 {

		reg = <0xf 0xe000a000 0 0x1000>;

		ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000

			  0x1000000 0x0 0x00000000 0xf 0xe3000000 0x0 0x100000>;

		pcie@0 {

			ranges = <0x2000000 0x0 0xa0000000

				  0x2000000 0x0 0xa0000000

				  0x0 0x20000000



				  0x1000000 0x0 0x0

				  0x1000000 0x0 0x0

				  0x0 0x100000>;

		};

	};



	rio: rapidio@fe00c0000 {

		reg = <0xf 0xe00c0000 0x0 0x20000>;

		port1 {

			ranges = <0x0 0x0 0xc 0x40000000 0x0 0x20000000>;

		};

	};

};



/*

 * mpc8548cds.dtsi must be last to ensure board_pci0 overrides pci0 settings

 * for interrupt-map & interrupt-map-mask.

 */



/include/ "mpc8548si-post.dtsi"

/include/ "mpc8548cds.dtsi"