Commit b9b43ad3 authored by Selvin Xavier's avatar Selvin Xavier Committed by Jason Gunthorpe
Browse files

RDMA/bnxt_re: Reduce the delay in polling for hwrm command completion 

Driver has 1ms delay between the polling for atomic command completion.
Polling immediately after issuing command usually doesn't report any
completions. So all commands in the blocking path needs two iterations. So
effectively 1ms spend on each command. HW requires much lesser time for
each command. So reduce the delay to 1us and increase the iteration count
to wait for the same time.

Link: https://lore.kernel.org/r/1631709163-2287-5-git-send-email-selvin.xavier@broadcom.com


Reviewed-by: default avatarLeon Romanovsky <leonro@nvidia.com>
Signed-off-by: default avatarSelvin Xavier <selvin.xavier@broadcom.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
parent 403bc435

drivers/infiniband/hw/bnxt_re/qplib_rcfw.c

+1 −1
Original line number Diff line number Diff line
@@ -78,7 +78,7 @@ static int __block_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie) 
	if (!test_bit(cbit, cmdq->cmdq_bitmap))

		goto done;

	do {

		mdelay(1); /* 1m sec */

		udelay(1);

		bnxt_qplib_service_creq(&rcfw->creq.creq_tasklet);

	} while (test_bit(cbit, cmdq->cmdq_bitmap) && --count);

done:

drivers/infiniband/hw/bnxt_re/qplib_rcfw.h

+1 −1
Original line number Diff line number Diff line
@@ -96,7 +96,7 @@ static inline void bnxt_qplib_set_cmd_slots(struct cmdq_base *req) 


#define RCFW_MAX_COOKIE_VALUE		0x7FFF

#define RCFW_CMD_IS_BLOCKING		0x8000

#define RCFW_BLOCKED_CMD_WAIT_COUNT	0x4E20

#define RCFW_BLOCKED_CMD_WAIT_COUNT	20000000UL /* 20 sec */



#define HWRM_VERSION_RCFW_CMDQ_DEPTH_CHECK 0x1000900020011ULL