Commit ba640cd3 authored by Vinod Koul's avatar Vinod Koul Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8450: Add qup nodes for qup2 



qup2 has 7 SEs, so add the SEs (i2c and spi) along with pinconf for
these SEs

Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220414101630.1189052-6-vkoul@kernel.org
parent 1a380216

arch/arm64/boot/dts/qcom/sm8450.dtsi

+396 −0
Original line number Diff line number Diff line
@@ -744,6 +744,299 @@ gpi_dma2: dma-controller@800000 { 
			status = "disabled";

		};



		qupv3_id_2: geniqup@8c0000 {

			compatible = "qcom,geni-se-qup";

			reg = <0x0 0x008c0000 0x0 0x2000>;

			clock-names = "m-ahb", "s-ahb";

			clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,

				 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;

			iommus = <&apps_smmu 0x483 0x0>;

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;

			status = "disabled";



			i2c15: i2c@880000 {

				compatible = "qcom,geni-i2c";

				reg = <0x0 0x00880000 0x0 0x4000>;

				clock-names = "se";

				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;

				pinctrl-names = "default";

				pinctrl-0 = <&qup_i2c15_data_clk>;

				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;

				#address-cells = <1>;

				#size-cells = <0>;

				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,

						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,

						<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;

				interconnect-names = "qup-core", "qup-config", "qup-memory";

				dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,

				       <&gpi_dma2 1 0 QCOM_GPI_I2C>;

				dma-names = "tx", "rx";

				status = "disabled";

			};



			spi15: spi@880000 {

				compatible = "qcom,geni-spi";

				reg = <0x0 0x00880000 0x0 0x4000>;

				clock-names = "se";

				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;

				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;

				pinctrl-names = "default";

				pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;

				spi-max-frequency = <50000000>;

				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,

						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;

				interconnect-names = "qup-core", "qup-config";

				dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,

				       <&gpi_dma2 1 0 QCOM_GPI_SPI>;

				dma-names = "tx", "rx";

				#address-cells = <1>;

				#size-cells = <0>;

				status = "disabled";

			};



			i2c16: i2c@884000 {

				compatible = "qcom,geni-i2c";

				reg = <0x0 0x00884000 0x0 0x4000>;

				clock-names = "se";

				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;

				pinctrl-names = "default";

				pinctrl-0 = <&qup_i2c16_data_clk>;

				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;

				#address-cells = <1>;

				#size-cells = <0>;

				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,

						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,

						<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;

				interconnect-names = "qup-core", "qup-config", "qup-memory";

				dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,

				       <&gpi_dma2 1 1 QCOM_GPI_I2C>;

				dma-names = "tx", "rx";

				status = "disabled";

			};



			spi16: spi@884000 {

				compatible = "qcom,geni-spi";

				reg = <0x0 0x00884000 0x0 0x4000>;

				clock-names = "se";

				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;

				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;

				pinctrl-names = "default";

				pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;

				spi-max-frequency = <50000000>;

				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,

						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;

				interconnect-names = "qup-core", "qup-config";

				dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,

				       <&gpi_dma2 1 1 QCOM_GPI_SPI>;

				dma-names = "tx", "rx";

				#address-cells = <1>;

				#size-cells = <0>;

				status = "disabled";

			};



			i2c17: i2c@888000 {

				compatible = "qcom,geni-i2c";

				reg = <0x0 0x00888000 0x0 0x4000>;

				clock-names = "se";

				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;

				pinctrl-names = "default";

				pinctrl-0 = <&qup_i2c17_data_clk>;

				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;

				#address-cells = <1>;

				#size-cells = <0>;

				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,

						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,

						<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;

				interconnect-names = "qup-core", "qup-config", "qup-memory";

				dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,

				       <&gpi_dma2 1 2 QCOM_GPI_I2C>;

				dma-names = "tx", "rx";

				status = "disabled";

			};



			spi17: spi@888000 {

				compatible = "qcom,geni-spi";

				reg = <0x0 0x00888000 0x0 0x4000>;

				clock-names = "se";

				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;

				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;

				pinctrl-names = "default";

				pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;

				spi-max-frequency = <50000000>;

				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,

						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;

				interconnect-names = "qup-core", "qup-config";

				dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,

				       <&gpi_dma2 1 2 QCOM_GPI_SPI>;

				dma-names = "tx", "rx";

				#address-cells = <1>;

				#size-cells = <0>;

				status = "disabled";

			};



			i2c18: i2c@88c000 {

				compatible = "qcom,geni-i2c";

				reg = <0x0 0x0088c000 0x0 0x4000>;

				clock-names = "se";

				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;

				pinctrl-names = "default";

				pinctrl-0 = <&qup_i2c18_data_clk>;

				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;

				#address-cells = <1>;

				#size-cells = <0>;

				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,

						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,

						<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;

				interconnect-names = "qup-core", "qup-config", "qup-memory";

				dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,

				       <&gpi_dma2 1 3 QCOM_GPI_I2C>;

				dma-names = "tx", "rx";

				status = "disabled";

			};



			spi18: spi@88c000 {

				compatible = "qcom,geni-spi";

				reg = <0 0x0088c000 0 0x4000>;

				clock-names = "se";

				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;

				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;

				pinctrl-names = "default";

				pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;

				spi-max-frequency = <50000000>;

				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,

						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;

				interconnect-names = "qup-core", "qup-config";

				dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,

				       <&gpi_dma2 1 3 QCOM_GPI_I2C>;

				dma-names = "tx", "rx";

				#address-cells = <1>;

				#size-cells = <0>;

				status = "disabled";

			};



			i2c19: i2c@890000 {

				compatible = "qcom,geni-i2c";

				reg = <0x0 0x00890000 0x0 0x4000>;

				clock-names = "se";

				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;

				pinctrl-names = "default";

				pinctrl-0 = <&qup_i2c19_data_clk>;

				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;

				#address-cells = <1>;

				#size-cells = <0>;

				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,

						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,

						<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;

				interconnect-names = "qup-core", "qup-config", "qup-memory";

				dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,

				       <&gpi_dma2 1 4 QCOM_GPI_I2C>;

				dma-names = "tx", "rx";

				status = "disabled";

			};



			spi19: spi@890000 {

				compatible = "qcom,geni-spi";

				reg = <0 0x00890000 0 0x4000>;

				clock-names = "se";

				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;

				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;

				pinctrl-names = "default";

				pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;

				spi-max-frequency = <50000000>;

				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,

						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;

				interconnect-names = "qup-core", "qup-config";

				dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,

				       <&gpi_dma2 1 4 QCOM_GPI_I2C>;

				dma-names = "tx", "rx";

				#address-cells = <1>;

				#size-cells = <0>;

				status = "disabled";

			};



			i2c20: i2c@894000 {

				compatible = "qcom,geni-i2c";

				reg = <0x0 0x00894000 0x0 0x4000>;

				clock-names = "se";

				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;

				pinctrl-names = "default";

				pinctrl-0 = <&qup_i2c20_data_clk>;

				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;

				#address-cells = <1>;

				#size-cells = <0>;

				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,

						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,

						<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;

				interconnect-names = "qup-core", "qup-config", "qup-memory";

				dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,

				       <&gpi_dma2 1 5 QCOM_GPI_I2C>;

				dma-names = "tx", "rx";

				status = "disabled";

			};



			spi20: spi@894000 {

				compatible = "qcom,geni-spi";

				reg = <0 0x00894000 0 0x4000>;

				clock-names = "se";

				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;

				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;

				pinctrl-names = "default";

				pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;

				spi-max-frequency = <50000000>;

				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,

						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;

				interconnect-names = "qup-core", "qup-config";

				dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,

				       <&gpi_dma2 1 5 QCOM_GPI_SPI>;

				dma-names = "tx", "rx";

				#address-cells = <1>;

				#size-cells = <0>;

				status = "disabled";

			};



			i2c21: i2c@898000 {

				compatible = "qcom,geni-i2c";

				reg = <0x0 0x00898000 0x0 0x4000>;

				clock-names = "se";

				clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;

				pinctrl-names = "default";

				pinctrl-0 = <&qup_i2c21_data_clk>;

				interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;

				#address-cells = <1>;

				#size-cells = <0>;

				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,

						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,

						<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;

				interconnect-names = "qup-core", "qup-config", "qup-memory";

				dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,

				       <&gpi_dma2 1 6 QCOM_GPI_I2C>;

				dma-names = "tx", "rx";

				status = "disabled";

			};



			spi21: spi@898000 {

				compatible = "qcom,geni-spi";

				reg = <0 0x00898000 0 0x4000>;

				clock-names = "se";

				clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;

				interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;

				pinctrl-names = "default";

				pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;

				spi-max-frequency = <50000000>;

				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,

						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;

				interconnect-names = "qup-core", "qup-config";

				dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,

				       <&gpi_dma2 1 6 QCOM_GPI_SPI>;

				dma-names = "tx", "rx";

				#address-cells = <1>;

				#size-cells = <0>;

				status = "disabled";

			};

		};



		gpi_dma0: dma-controller@900000 {

			compatible = "qcom,sm8450-gpi-dma";

			#dma-cells = <3>;
@@ -2174,6 +2467,41 @@ qup_i2c14_data_clk: qup-i2c14-data-clk { 
				bias-pull-up;

			};



			qup_i2c15_data_clk: qup-i2c15-data-clk {

				pins = "gpio56", "gpio57";

				function = "qup15";

			};



			qup_i2c16_data_clk: qup-i2c16-data-clk {

				pins = "gpio60", "gpio61";

				function = "qup16";

			};



			qup_i2c17_data_clk: qup-i2c17-data-clk {

				pins = "gpio64", "gpio65";

				function = "qup17";

			};



			qup_i2c18_data_clk: qup-i2c18-data-clk {

				pins = "gpio68", "gpio69";

				function = "qup18";

			};



			qup_i2c19_data_clk: qup-i2c19-data-clk {

				pins = "gpio72", "gpio73";

				function = "qup19";

			};



			qup_i2c20_data_clk: qup-i2c20-data-clk {

				pins = "gpio76", "gpio77";

				function = "qup20";

			};



			qup_i2c21_data_clk: qup-i2c21-data-clk {

				pins = "gpio80", "gpio81";

				function = "qup21";

			};



			qup_spi0_cs: qup-spi0-cs {

				pins = "gpio3";

				function = "qup0";
@@ -2326,6 +2654,74 @@ qup_spi15_data_clk: qup-spi15-data-clk { 
				function = "qup15";

			};



			qup_spi16_cs: qup-spi16-cs {

				pins = "gpio63";

				function = "qup16";

			};



			qup_spi16_data_clk: qup-spi16-data-clk {

				pins = "gpio60", "gpio61", "gpio62";

				function = "qup16";

			};



			qup_spi17_cs: qup-spi17-cs {

				pins = "gpio67";

				function = "qup17";

			};



			qup_spi17_data_clk: qup-spi17-data-clk {

				pins = "gpio64", "gpio65", "gpio66";

				function = "qup17";

			};



			qup_spi18_cs: qup-spi18-cs {

				pins = "gpio71";

				function = "qup18";

				drive-strength = <6>;

				bias-disable;

			};



			qup_spi18_data_clk: qup-spi18-data-clk {

				pins = "gpio68", "gpio69", "gpio70";

				function = "qup18";

				drive-strength = <6>;

				bias-disable;

			};



			qup_spi19_cs: qup-spi19-cs {

				pins = "gpio75";

				function = "qup19";

				drive-strength = <6>;

				bias-disable;

			};



			qup_spi19_data_clk: qup-spi19-data-clk {

				pins = "gpio72", "gpio73", "gpio74";

				function = "qup19";

				drive-strength = <6>;

				bias-disable;

			};



			qup_spi20_cs: qup-spi20-cs {

				pins = "gpio79";

				function = "qup20";

			};



			qup_spi20_data_clk: qup-spi20-data-clk {

				pins = "gpio76", "gpio77", "gpio78";

				function = "qup20";

			};



			qup_spi21_cs: qup-spi21-cs {

				pins = "gpio83";

				function = "qup21";

			};



			qup_spi21_data_clk: qup-spi21-data-clk {

				pins = "gpio80", "gpio81", "gpio82";

				function = "qup21";

			};



			qup_uart7_rx: qup-uart7-rx {

				pins = "gpio26";

				function = "qup7";