Skip to content
Commit bd348ca2 authored by Xingyu Wu's avatar Xingyu Wu Committed by Conor Dooley
Browse files

dt-bindings: clock: Add StarFive JH7110 PLL clock generator



Add bindings for the PLL clock generator on the JH7110 RISC-V SoC.

Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarXingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: default avatarEmil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 06c2afb8
Loading
Loading
Loading
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please to comment