Commit bdf44733 authored by Rodrigo Siqueira's avatar Rodrigo Siqueira Committed by Alex Deucher
Browse files

drm/amd/display: Create patch bounding box function for isolate FPU 



In the DCN30 resource, we have a small patch to the bounding box struct;
this patch uses FPU operations. This commit moves that specific part to
its function under the DML folder.

Reviewed-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Acked-by: default avatarAlex Hung <alex.hung@amd.com>
Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 05674cc9

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c

+2 −17
Original line number Original line Diff line number Diff line
@@ -1521,26 +1521,11 @@ static bool init_soc_bounding_box(struct dc *dc, 
	loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;

	loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;

	loaded_ip->max_num_dpp = pool->base.pipe_count;

	loaded_ip->max_num_dpp = pool->base.pipe_count;

	loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;

	loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;



	DC_FP_START();

	dcn20_patch_bounding_box(dc, loaded_bb);

	dcn20_patch_bounding_box(dc, loaded_bb);

	DC_FP_START();

	patch_dcn30_soc_bounding_box(dc, &dcn3_0_soc);

	DC_FP_END();

	DC_FP_END();





	if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

		struct bp_soc_bb_info bb_info = {0};



		if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {

			if (bb_info.dram_clock_change_latency_100ns > 0)

				dcn3_0_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;



			if (bb_info.dram_sr_enter_exit_latency_100ns > 0)

				dcn3_0_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;



			if (bb_info.dram_sr_exit_latency_100ns > 0)

				dcn3_0_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;

		}

	}



	return true;

	return true;

}

}

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

+20 −0
Original line number Original line Diff line number Diff line
@@ -721,3 +721,23 @@ void dcn3_fpu_build_wm_range_table(struct clk_mgr *base) 
	base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;

	base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;

	base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;

	base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;

}

}



void patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *dcn3_0_ip)

{

	dc_assert_fp_enabled();



	if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

		struct bp_soc_bb_info bb_info = {0};



		if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {

			if (bb_info.dram_clock_change_latency_100ns > 0)

				dcn3_0_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;



			if (bb_info.dram_sr_enter_exit_latency_100ns > 0)

				dcn3_0_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;



			if (bb_info.dram_sr_exit_latency_100ns > 0)

				dcn3_0_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;

		}

	}

}

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -71,4 +71,6 @@ int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, 




void dcn3_fpu_build_wm_range_table(struct clk_mgr *base);

void dcn3_fpu_build_wm_range_table(struct clk_mgr *base);





void patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *dcn3_0_ip);



#endif /* __DCN30_FPU_H__*/
 
#endif /* __DCN30_FPU_H__*/