Commit be525de9 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

pinctrl: renesas: r8a77990: Optimize fixed-width reserved fields 



Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 226 bytes.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/924ba4505e33180e078ca72a1db8db13c193cbea.1649865241.git.geert+renesas@glider.be
parent 23dbafd8

drivers/pinctrl/renesas/pfc-r8a77990.c

+29 −92
Original line number Diff line number Diff line
@@ -4603,21 +4603,11 @@ static const struct { 
static const struct pinmux_cfg_reg pinmux_config_regs[] = {

#define F_(x, y)	FN_##y

#define FM(x)		FN_##x

	{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,

			     GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1, 1),

			     GROUP(

		/* GP0_31_18 RESERVED */

		GP_0_17_FN,	GPSR0_17,

		GP_0_16_FN,	GPSR0_16,

		GP_0_15_FN,	GPSR0_15,
@@ -4637,16 +4627,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_0_1_FN,	GPSR0_1,

		GP_0_0_FN,	GPSR0_0, ))

	},

	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR1", 0xe6060104, 32,

			     GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),

			     GROUP(

		/* GP1_31_23 RESERVED */

		GP_1_22_FN,	GPSR1_22,

		GP_1_21_FN,	GPSR1_21,

		GP_1_20_FN,	GPSR1_20,
@@ -4705,23 +4690,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_2_1_FN,	GPSR2_1,

		GP_2_0_FN,	GPSR2_0, ))

	},

	{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,

			     GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1),

			     GROUP(

		/* GP3_31_16 RESERVED */

		GP_3_15_FN,	GPSR3_15,

		GP_3_14_FN,	GPSR3_14,

		GP_3_13_FN,	GPSR3_13,
@@ -4739,28 +4712,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_3_1_FN,	GPSR3_1,

		GP_3_0_FN,	GPSR3_0, ))

	},

	{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,

			     GROUP(-21, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),

			     GROUP(

		/* GP4_31_11 RESERVED */

		GP_4_10_FN,	GPSR4_10,

		GP_4_9_FN,	GPSR4_9,

		GP_4_8_FN,	GPSR4_8,
@@ -4773,19 +4728,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_4_1_FN,	GPSR4_1,

		GP_4_0_FN,	GPSR4_0, ))

	},

	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,

			     GROUP(-12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1, 1, 1, 1),

			     GROUP(

		/* GP5_31_20 RESERVED */

		GP_5_19_FN,	GPSR5_19,

		GP_5_18_FN,	GPSR5_18,

		GP_5_17_FN,	GPSR5_17,
@@ -4807,21 +4754,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_5_1_FN,	GPSR5_1,

		GP_5_0_FN,	GPSR5_0, ))

	},

	{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR6", 0xe6060118, 32,

			     GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1, 1),

			     GROUP(

		/* GP6_31_18 RESERVED */

		GP_6_17_FN,	GPSR6_17,

		GP_6_16_FN,	GPSR6_16,

		GP_6_15_FN,	GPSR6_15,